Methods of forming trench isolation structures by etching...

Details Methods of forming trench isolation structures by etching... Methods of forming trench isolation structures by etching...

1998-12-18

2001-01-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S435000

Utility Patent

active

06169002

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits in general and more particularly to the fabrication of integrated circuit substrates.
BACKGROUND OF THE INVENTION
Conventional integrated circuits may use a Local Oxidation of Silicon process (LOCOS) to isolate active devices of the integrated circuits. The LOCOS process may, however, create defects in the integrated circuit, such as bird's beaks, as the level of integration of the integrated circuit rises. A technique known as trench isolation may be used to reduce the defects associated with the LOCOS process. Trench isolation techniques may, however, produce other defects in the integrated circuit that can increase device leakage currents, thereby possibly decreasing the reliability of the gate oxide layer of the active device.
FIG. 1A through 1C
are enlarged cross-sectional views of structures that illustrate conventional methods of forming integrated circuit substrates containing trench isolation regions.
FIG. 1A
is an enlarged cross-sectional view of an integrated circuit substrate including a conventional trench isolation layer
18
on a semiconductor substrate
10
. In particular, a pad oxide layer
12
and a silicon nitride layer
13
are sequentially formed on the semiconductor substrate
10
. The pad oxide layer
12
and the silicon nitride layer
13
are patterned and etched to form a mask
14
that exposes regions of the semiconductor substrate
10
which are to be electrically inactive (which will subsequently be formed into isolation regions). The exposed regions of the semiconductor substrate
10
are selectively etched to form a plurality of trenches
16
in the semiconductor substrate
10
, using the mask
14
as an etching mask.
A trench isolation material, such as an oxide layer, is formed in each trench
16
and planarized to form the trench isolation layer
18
. The planarization may be performed using Chemical Mechanical Polishing (CMP). During the planarization process the patterned silicon nitride layer, which has an etch selectivity ratio in a range between about 1:3 and 1:4 with respect to the trench isolation layer
18
, acts as a polishing stop layer.
Referring to
FIG. 1B
, the mask
14
is removed using an etchant, which may cause defects to an edge portion
20
of the trench
16
located at the interface of the trench isolation layer
18
and the semiconductor substrate
10
. Removing the mask
14
leaves a protrusion of the trench isolation layer
18
from the semiconductor substrate
10
. The semiconductor substrate
10
is then cleaned using an isotropic wet chemical process. Unfortunately, like the etchant used to remove the mask
14
, the wet chemical process may attack the trench isolation layer
18
at the edge portion
20
of the trench
16
as shown in FIG.
1
C.
Referring to
FIG. 1D
, if the edge portion
20
is etched away by an additional isotropic wet chemical process, grooves may be formed in the trench isolation layer
18
, thereby possibly degrading the characteristics of the trench isolation layer
18
. Moreover, the grooves may be enlarged by subsequent cleaning steps, possibly further degrading the characteristics of the trench isolation layer
18
. Conventional methods of reducing the formation of the grooves described above are discussed in U.S. Pat. No. 5,837,612 to Ajuria et al.; U.S. Pat. No. 5,817,566 to Jang et al.; U.S. Pat. No. 5,811,345 to Yu et al.; U.S. Pat. No. 5,804,491 to Ahn; U.S. Pat. No. 5,786,262 to Jang et al.; U.S. Pat. No. 5,741,740 to Jang et al.; U.S. Pat. No. 5,728,620 to Park; U.S. Pat. No. 5,726,090 to Jang et al.; U.S. Pat. No. 5,712,205 to Park et al.; U.S. Pat. No. 5,679,599 to Mehta; U.S. Pat. No. 5,665,635 to Kwon et al.; U.S. Pat. No. 5,372,950 to Kim et al.; U.S. Pat. No. 5,360,753 to Park et al.; and U.S. Pat. No. 4,636,281 to Buiguez et al. According to Ajuria et al., CMP stops are replaced with polysilicon polish stops which may be more effective in reducing the grooves caused by the wet etching process.
In view of the above, there continues to be a need to improve methods of forming trench isolation structures in integrated circuits.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to allow an improvement in the formation of trench isolation structures in integrated circuits.
It is another object of the present invention to improve the reliability of integrated circuits having trench isolation structures.
These and other objects of the present invention are provided by forming an electrically insulating layer in a trench using a mask and using the mask to etch back the electrically insulating layer. Etching back the electrically insulating layer using the mask may prevent a protrusion of the electrically insulating layer associated with the prior art and reduce the likelihood of grooves forming on the surface of the electrically insulating layer upon the subsequent performance of a wet etching step.
In another aspect of the present invention, the electrically insulating layer is etched back using the mask as a planarization stop and then etching the planarized electrically insulating layer using the mask as an etching mask.
In another aspect of the present invention, the mask comprises a pad oxide layer formed on the semiconductor substrate and a planarization stop layer formed on the pad oxide layer. The planarization stop layer comprises an organic material such as SOG or a polymer layer. The etch rate of the organic material is slow compared to the electrically insulating layer. Consequently, the planarization of the mask and the electrically insulating layer can be controlled because the (organic) planarization stop layer will be etched more slowly than the trench isolation material.
In a further aspect of the present invention, the organic material is made inorganic by exposure to oxygen or by evaporating the organic material. The inorganized material may thereby be etched more easily to complete the trench isolation structure.


REFERENCES:
patent: 4636281 (1987-01-01), Buiguez et al.
patent: 5360753 (1994-11-01), Park et al.
patent: 5372950 (1994-12-01), Kim et al.
patent: 5665635 (1997-09-01), Kwon et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5712205 (1998-01-01), Park et al.
patent: 5726090 (1998-03-01), Jang et al.
patent: 5728620 (1998-03-01), Park
patent: 5741740 (1998-04-01), Jang et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5804491 (1998-09-01), Ahn
patent: 5811345 (1998-09-01), Yu et al.
patent: 5817566 (1998-10-01), Jang et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5994201 (2000-06-01), Lee
patent: 6063694 (2000-05-01), Togo
patent: 6071792 (2000-06-01), Kim et al.
patent: 6087243 (2000-07-01), Wang

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