Methods of forming output prediction logic circuits with...

Details Methods of forming output prediction logic circuits with... Methods of forming output prediction logic circuits with...

2006-02-14

2006-02-14

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S272000, C438S589000, C438S590000

Reexamination Certificate

active

06998311

ABSTRACT:
Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

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