Methods of forming nonvolatile memory devices using improved...

Details Methods of forming nonvolatile memory devices using improved... Methods of forming nonvolatile memory devices using improved...

1999-06-10

2001-02-06

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000

Reexamination Certificate

active

06184085

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit device fabrication methods and devices formed thereby, and more particularly to methods of forming integrated circuit memory devices and devices formed thereby.
BACKGROUND OF THE INVENTION
Nonvolatile memory devices such as the EPROM device are widely used as unit cells of integrated circuit memory devices. As illustrated by
FIGS. 1
a
-
1
b
, a unit cell EPROM device (“I”) according to the prior art includes a semiconductor substrate
10
having a plurality of field oxide isolation regions
12
therein and a plurality of gate oxide insulating layers
14
a
on a surface thereof. Floating gate electrodes
16
a
of the EPROM memory cell are also provided on the gate oxide insulating layers
14
a
. In addition, an electrically insulating oxide
itride/oxide (ONO) capping layer
20
is provided on the floating gate electrodes
16
a
. A polycide control gate electrode
24
is also provided on a row of floating gate electrodes
16
a
and acts as a word line of the memory device.
Referring now to
FIGS. 2-7
, a method of forming the prior art memory device of
FIGS. 1
a
-
1
b
will now be described. In
FIGS. 2-7
, the portions of the substrate
10
designated by reference numeral “A” represent memory cell array portions of the substrate
10
and the portions of the substrate
10
designated by reference numeral “B” represent peripheral circuit portions of the substrate
10
. As illustrated by
FIG. 2
, the prior art method includes the step of forming a plurality of field oxide isolation regions
12
on the semiconductor substrate
10
. The portions of the substrate
10
that are not covered by the field oxide isolation regions
12
may comprise active regions. A thermal oxidation step may then be performed to define first gate insulating layers
14
a
on the active regions. A blanket layer of polysilicon is then deposited as a first electrically conductive layer
16
. Next, a first photoresist pattern
18
a
may be formed on the first electrically conductive layer
16
.
Referring now to
FIG. 3
, the first electrically conductive layer
16
may then be dry-etched to define a floating gate electrode
16
a
, using the first photoresist pattern
18
a
as an etching mask. The first photoresist pattern
18
a
is then removed. Next, a blanket layer of an electrically insulating layer
20
, which may comprise an oxide-nitride-oxide (ONO) composite insulating layer, is deposited. A blanket photoresist layer is then deposited on the electrically insulating layer
20
. Conventional photolithography steps may then be performed to convert the blanket photoresist layer into a second photoresist pattern
18
b
on the memory cell array portion “A” of the substrate.
Referring now to
FIG. 4
, an etching step is then performed to remove the portion of the electrically insulating layer
20
extending opposite the peripheral circuit portion “B” of the substrate
10
. During this etching step, a portion of the first gate insulating layer
14
a
on the peripheral circuit portion “B” of the substrate may also be etched somewhat. As illustrated best by
FIG. 5
, a wet etching step is then performed to remove the first gate insulating layer
14
a
from the peripheral circuit portion “B” of the substrate
10
. This etching step is performed using the second photoresist pattern
18
b
as an etching mask. Next, a blanket layer
22
of an electrically conductive material (e.g., polycide) is then deposited on the substrate
10
.
Referring now to
FIG. 6
, a third photoresist pattern
18
c
is then formed on the peripheral circuit portion “B” of the substrate
10
using conventional techniques. A dry etching step is then performed to convert the blanket layer
22
of second electrically conductive material into a plurality of control electrodes
24
(e.g., word lines) having the shapes illustrated by
FIG. 1
a
. Referring now to
FIG. 7
, the third photoresist pattern
18
c
is removed and followed by the step of forming a fourth photoresist pattern
18
d
on the substrate
10
. This fourth photoresist pattern
18
d
exposes the peripheral circuit portion “B” of the substrate
10
. Another etching step (e.g., dry etching step) is then performed to convert a portion of the blanket layer
22
on the peripheral circuit portion “B” of the substrate
10
into a gate electrode
26
. The fourth photoresist pattern
18
d
is then removed.
Unfortunately, the use of four masks in the method of
FIGS. 2-7
can limit process yield and increase manufacturing costs. Thus, notwithstanding the above-described method, there continues to be a need for improved methods of forming integrated circuit memory devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming integrated circuit devices and devices formed thereby.
It is another object of the present invention to provide methods of forming integrated circuit memory devices having floating gate electrodes and memory devices formed thereby.
It is still another object of the present invention to provide methods of forming integrated circuit memory devices using a reduced number of photolithographically defined masking steps and devices formed thereby.
These and other objects, advantages and features of the present invention are provided by preferred methods of forming integrated circuit memory devices having floating gate electrodes, using a reduced number of photolithographically defined etching steps. These preferred methods include the steps of forming a plurality of field oxide isolation regions on a semiconductor substrate. A thermal oxidation step may then be performed to define first gate insulating layers on active regions within the substrate. A blanket layer of polysilicon is then deposited as a first electrically conductive layer. Next, a blanket layer of an electrically insulating layer, which may comprise an oxide-nitride-oxide (ONO) composite insulating layer, is deposited. A blanket photoresist layer is then deposited on the electrically insulating layer. Conventional photolithography steps may then be performed to convert the blanket photoresist layer into a photoresist pattern on a memory cell array portion of the substrate.
A dry etching step is then performed to define a floating gate electrode having an ONO electrically insulating cap thereon, on the memory cell array portion of the substrate. During this etching step, a portion of the first gate insulating layer on a peripheral circuit portion of the substrate may also be etched somewhat. In particular, after the dry etching step, the thickness of the first gate insulating layer on the peripheral circuit portion of the substrate may be reduced by about 20-30% of its original thickness. A wet etching step is then performed to remove the first gate insulating layer from the peripheral circuit portion of the substrate. This wet etching step is performed using the same mask (i.e., photoresist pattern) that was used during the dry etching step. During this wet etching step, portions of the field oxide isolation regions are also etched in the memory cell array portion of the substrate. In particular, the wet etching step causes portions of the floating gate electrodes to be undercut as portions of the underlying field oxide isolation regions are etched.
After the photoresist pattern is removed, a thermal oxidation step is then performed to grow a second gate insulating layer on the peripheral circuit portion of the substrate and grow sidewall insulating spacers on the sidewalls and undercut portions of the floating gate electrodes. Based on this thermal oxidation step, the floating gate electrodes become encapsulated by electrically insulating material. A blanket layer of a second electrically conductive material (e.g., polycide) is then deposited on the substrate. A second photoresist pattern is then formed on the peripheral circuit portion of the substrate using conventional techniques. This second photoresist pattern also extends onto the memory cell array portion of the substrate.

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