Methods of forming nonvolatile integrated circuit memory...

Details Methods of forming nonvolatile integrated circuit memory... Methods of forming nonvolatile integrated circuit memory...

1997-09-17

2001-03-20

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C438S265000, C438S594000

Reexamination Certificate

active

06204122

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of forming integrated circuits and more particularly to methods of forming integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Nonvolatile memory devices such as EEPROM or flash EEPROM devices typically have a floating gate in which data is retained and a control gate to which a control voltage is applied, on a semiconductor substrate having source and drain regions therein.
FIGS. 1A-1B
are sectional views showing a conventional EEPROM device, in which
FIG. 1A
is a sectional view taken along a word line, and
FIG. 1B
is a sectional view taken along a bit line. Referring to
FIGS. 1A-1B
, a plurality of active regions and a plurality of field regions are sequentially disposed parallel to each other on a semiconductor substrate
10
. A tunnel oxide layer
16
is formed on the active regions and an isolation layer
12
for isolating the active regions is formed on the field regions. A channel stop layer
14
for strengthening isolating characteristics is formed under the isolation layer
12
, as illustrated. A rectangular floating gate
18
patterned to be extended to the edges of the isolation layer
12
, is formed on the tunnel oxide layer
16
, and an interlayer insulation film
22
of ONO (oxide
itride/oxide) is formed on the floating gate
18
. A control gate
24
is formed on the interlayer insulation film
22
. Also, source and drain regions
20
are formed on the semiconductor substrate between the floating gates of adjacent unit cell transistors, as illustrated best by FIG.
1
B.
FIGS. 2A and 2B
are layout views showing the sequence of steps in a conventional EEPROM manufacturing process. In
FIG. 2A
, the area indicated by a dashed line represents a first mask pattern P
1
for forming the active region of a semiconductor substrate, and an oblique-lined area represents a second mask pattern P
2
for forming a floating gate. In
FIG. 2B
, the area indicated by a solid line represents a third mask pattern P
3
for forming a control gate.
As used herein, a direction along the line III—III of
FIG. 2A
is called a word line direction, and a direction along the line III′—III′ is called a bit line direction. Also, the floating gate of the second mask pattern P
2
is extended to the field region (the region between first mask patterns of adjacent unit cell transistors) as well as the active regions (the regions of the first mask patterns P
1
).
FIGS. 3A and 3B
are sectional views taken along the lines III—III and III′—III′ of
FIG. 2A
, and
FIGS. 4A and 4B
are sectional views taken along the lines IV—IV and IV′—IV′ of FIG.
2
B. First, referring to
FIGS. 3A and 3B
, an N-type well and a P-type well (not shown) are sequentially formed on a P-type semiconductor substrate
10
. A channel stop layer
14
and an isolation film
12
are formed using a conventional isolation method such as a field ion implantation method, Local Oxidation of Silicon (LOCOS) or Selective Polysilicon Oxidation (SEPOX). Subsequently, a tunnel oxide layer
16
is formed on the active regions, polysilicon for a floating gate is deposited thereon using a conventional chemical vapor growth deposition (CVD) method, and then a floating gate pattern
17
is formed in a bit line direction during a photolithographic etching process using the second mask pattern P
2
of
FIG. 2A
as an etching mask.
Next, referring to
FIGS. 4A and 4B
, an interlayer insulation film
22
consisting of ONO is formed on the entire surface of the floating gate pattern
17
, and polysilicon and polycide for the control gate are sequentially deposited thereon. Then, the polysilicon and polycide for the control gate, interlayer insulation film
22
and floating gate pattern
17
are sequentially etched (by a self-alignment etching process), thereby forming a floating gate
18
, an interlayer insulation film
22
formed on the floating gate
18
, and a control gate
24
formed in a word line direction. The source and drain regions
20
may be formed by implanting impurity ions after forming the floating gate
18
and the control gate
24
.
As will be understood by those skilled in the art, EEPROM devices may be programmed by causing the forward tunneling of electrons from a drain or a bulk region, (e.g., a semiconductor substrate) to a floating gate, and erased by causing the reverse tunneling of electrons from the floating gate to the drain or bulk region. The program and erase operations will now be described in detail with reference to FIG.
1
. First, the program operation is performed to charge the floating gate
18
with electrons by applying a high voltage of about 18 volts to the control gate
24
. During the programming operations, the drain
20
is grounded and the source
20
is floated. Next, the erase operation is performed by transferring the electrons accumulated in the floating gate
18
to the drain
20
or bulk region. Here, a high voltage of about 18 volts is applied to the drain
20
, the control gate
24
is grounded, and the source
20
is floated so that electrons held by the floating gate
18
tunnel out to the drain
20
. Alternatively, a high voltage of about 18 volts is applied to the bulk region and the control gate
24
is grounded so that electrons tunnel from the floating gate
18
to the bulk region.
During these operations, the voltage induced on the floating gate
18
is determined by a ratio of the capacitance between the floating gate
18
and control gate
24
to the capacitance between the floating gate
18
and semiconductor substrate
10
. This capacitance ratio is called a coupling ratio.
As described above, since a high voltage is applied to the nonvolatile memory device during a program operation, isolation characteristics between active regions are important in determining device reliability. The factors which determine the isolation characteristics are the thickness and width of an isolation layer, the impurity concentration of a channel stop layer formed underneath the isolation layer, and the magnitude of the voltage supplied during the program operation. As the isolation spacing between active regions becomes narrower during device integration, these factors can become serious impediments to the ability to achieve high integration densities.
One of the methods for strengthening the device isolation characteristics is to thicken the isolation layer. However, as the degree of device integration is increased, the width of a field isolation region typically becomes smaller. Thus, increasing the thickness of an isolation layer to be grown in a reduced field region has a limited effect. As another method for strengthening device insulation characteristics, the impurity concentration of a device isolating channel stop layer may be increased. This method, however, has several disadvantages since the breakdown characteristics may be deteriorated at the points where the source/drain and a channel stop layer meet, and because the channel stop layer is typically extended into the cell active region by a subsequent thermal process to reduce the width of the cell active region, which lowers cell current.
Another method of strengthening the device isolation characteristics includes reducing the voltage applied to the control gate during programming operations and increasing the coupling ratio so that the voltage appearing between the floating gate and substrate is maintained at a high level to promote tunneling. This increase in coupling ratio also allows the voltage induced to both ends of the tunnel oxide layer to be kept constant. Thus, since a programmable cell is implemented at a lower program voltage, the thickness of the isolation layer can be reduced.
In order to increase the coupling ratio, there has been proposed a method for increasing the dielectric constant of the interlayer insulation film disposed between the floating gate and control gate; however, this requires a newly developed dielectric material. Alternatively, the thickness of the interlayer insulation film may be r

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