Methods of forming MOS transistors having hot-carrier suppressio

Details Methods of forming MOS transistors having hot-carrier suppressio Methods of forming MOS transistors having hot-carrier suppressio

1996-12-12

1998-11-24

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438300, 438305, 438233, H01L 218238, H01L 21336

Patent

active

058406042

ABSTRACT:
Methods of forming MOS transistors include the steps of forming hot-carrier suppression electrodes on opposing sides of an insulatedgate of a field effect transistor, to reduce hot-carrier degradation parasitics and reduce gate-to-drain overlap capacitance (C.sub.gd). These methods include the steps of forming at least a first hot-carrier suppression electrode between a drain electrode and an insulated gate electrode of a field effect transistor. The hot-carrier suppression electrode reduces the likelihood of hot-carrier degradation parasitics by inhibiting hot electron injection into the gate oxide of the field effect transistor and also reduces the gate-to-drain region capacitance by eliminating the need to establish a fully-overlapped geometry between the transistor's gate and lightly doped drain (LDD) region extension as a way to prevent parasitic injection. According to a preferred embodiment of the present invention, a first electrically insulating layer (e.g., SiO.sub.2) is initially formed on a face of a semiconductor substrate containing a region of first conductivity type (e.g., P-well, N-well) therein extending to the face. A first conductive layer (e.g., polysilicon) is also formed on the first electrically insulating layer, opposite the region of first conductivity type. The first conductive layer is then patterned to define first and second hot-carrier suppression electrodes having opposing sidewalls. These sidewalls are then oxidized and then a gate electrode is formed between the oxidized sidewalls. Source and drain regions of second conductivity type are then formed in the region of first conductivity type, opposite the first and second hot-carrier suppression electrodes, and then source and drain contacts are patterned to electrically contact the first and second hot-carrier suppression electrodes, respectively.

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patent: 5413948 (1995-05-01), Pfiester et al.
Huang et al., A New LDD Transistor With Inverse-T Gate Structure, IEEE Electron Device Letters, vol. EDL-8, No. 4, Apr. 1987, pp. 151-153.
Izawa et al., Impact Of The Gate-Drain Overlapped Device (GOLD) For Deep Submicrometer VLSI, IEEE Transactions on Electron Devices, vol. 35, No. 12, Dec. 1988, pp. 2088-2093.

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