Methods of forming mixed gate CMOS with single poly deposition

Details Methods of forming mixed gate CMOS with single poly deposition Methods of forming mixed gate CMOS with single poly deposition

Filed on

2007-11-06

Date issued

2010-06-22

Examiner

Parker, Kenneth A (Department: 2815)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C257SE21623, C257SE21625

Type

Reexamination Certificate

Status

active

Patent number

07741181

Description

ABSTRACT:
A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

REFERENCES:
patent: 6303418 (2001-10-01), Cha
patent: 7462520 (2008-12-01), Park et al.
patent: 2005/0153496 (2005-07-01), Ngo et al.
patent: 2006/0199324 (2006-09-01), Yu

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