Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-03-18
2010-06-15
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S645000, C438S687000, C257SE21579, C257SE21496
Reexamination Certificate
active
07737029
ABSTRACT:
Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.
REFERENCES:
patent: 6165894 (2000-12-01), Pramanick et al.
patent: 6225210 (2001-05-01), Ngo et al.
patent: 6333248 (2001-12-01), Kishimoto
patent: 6383925 (2002-05-01), Ngo et al.
patent: 6656832 (2003-12-01), Pan et al.
patent: 6734101 (2004-05-01), Bao et al.
patent: 6734102 (2004-05-01), Rathi et al.
patent: 6764940 (2004-07-01), Rozbicki et al.
patent: 6764952 (2004-07-01), Yu et al.
patent: 6797608 (2004-09-01), Lin
patent: 6797642 (2004-09-01), Chu et al.
patent: 6875694 (2005-04-01), Ngo et al.
patent: 6897144 (2005-05-01), Ngo et al.
patent: 6897147 (2005-05-01), Tsai et al.
patent: 6927159 (2005-08-01), Faust et al.
patent: 6946401 (2005-09-01), Huang et al.
patent: 7037835 (2006-05-01), Lee et al.
patent: 7037836 (2006-05-01), Lee
patent: 7094705 (2006-08-01), Lin et al.
patent: 7122484 (2006-10-01), Perng et al.
patent: 7158384 (2007-01-01), Yim et al.
patent: 7163889 (2007-01-01), Yu et al.
patent: 7205666 (2007-04-01), Lee et al.
patent: 7232766 (2007-06-01), Bailey, III et al.
patent: 7239017 (2007-07-01), Yu et al.
patent: 7282438 (2007-10-01), Yu et al.
patent: 2001/0049181 (2001-12-01), Rathi et al.
patent: 2003/0209738 (2003-11-01), Ohto et al.
patent: 2004/0161924 (2004-08-01), Chen et al.
patent: 2004/0175933 (2004-09-01), Shishida et al.
patent: 1020020053609 (2002-07-01), None
patent: 1020030030268 (2003-04-01), None
patent: 1020030052487 (2003-06-01), None
Bonilla Griselda
Kim Jae-hak
Molis Steven E.
Restaino Darryl D.
Shobha Hosadurga
Chartered Semiconductor Manufacturing Ltd.
Fourson George
International Business Machines - Corporation
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
LandOfFree
Methods of forming metal interconnect structures on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming metal interconnect structures on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming metal interconnect structures on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4161821