Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-09-28
2008-10-14
Graybill, David E (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S627000, C438S648000, C438S633000, C438S637000, C438S639000, C438S672000
Reexamination Certificate
active
07435673
ABSTRACT:
Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.
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Notice of Examination Report, Korean Application No. 10-2006-0001374, Nov. 15, 2006.
Hong Duk Ho
Ku Ja-Hum
Lee Kyoung Woo
Park Wan Jae
Graybill David E
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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