Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-16
2001-05-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S255000, C438S381000, C438S396000, C438S397000, C438S398000
Reexamination Certificate
active
06238968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing, and more particularly to a cylindrical capacitor with hemi-spherical grain(HSG) silicon on its inner surfaces and a method for fabricating thereof.
2. Description of the Related Art
With the recent increase of integration density of a DRAM, a cell size and an area to be occupied by a capacitor of the DRAM cell tend to reduce, respectively. The capacitor is made of two opposite electrodes and a dielectric film disposed therebetween. As well known in the art, capacitor needs a minimum level of charge storage capacitance.
The capacitance is related to the dielectric thickness, dielectric permittivity and available surface areas. As is well known, the capacitance is proportional to dielectric permittivity and available surface areas and inversely proportional to dielectric thickness.
One way to increase capacitance in a given cell area is to form a thin dielectric film. Another way is to use a high dielectric film having high dielectric permittivity such as BST. Alternative approach is to increase the surface areas of the capacitor by increasing the topology such as a stacked capacitor. Such stacked capacitors include, for examples double-stacked, fin stacked, cylindrical, spread-stacked, and box structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suitable for an integrated memory cell. Recently, new technologies have been developed for increasing the effective surface area by modifying the surface morphology of the polysilicon storage electrode itself by engraving or controlling the nucleation and growth condition of polysilicon. A hemispherical-grain(HSG) polysilicon layer can be deposited over a storage node to increase surfaces area and capacitance.
A reference is made to the U.S. Pat. No. 5,827,766 by Lou entitled as “Method for fabricating cylindrical capacitor for a memory cell”. The above cited reference forms HSG silicons on an inner surface of a cylindrical capacitor.
There are some problems with above cited reference and other methods for forming a cylindrical capacitor with HSG silicon. For example, HSG silicon may be sequestered from the capacitor after formation thereof during subsequent cleaning process using chemical etchant. As a result, sequestered HSG silicons degrade reliability of the capacitor.
Accordingly, there is a strong need for a method for forming a reliable capacitor with increased surface area in a given cell area by forming HSG silicon.
SUMMARY OF THE INVENTION
The present invention is directed toward providing a method for fabricating a reliable cylindrical capacitor having HSG silicon on its inner surfaces.
One of the features of the present invention is the formation of a silicon nitride layer on the HSG silicon in order to protect the HSG silicon during subsequent cleaning process. The silicon nitride layer can also be used as a dielectric component of nitride/oxide dielectric structure.
Briefly, in accordance with one aspect of the present invention, there is provided a method for fabricating a cylindrical capacitor which comprises forming a first insulating layer on an integrated circuit substrate. A contact plug is formed in the first insulating layer by the process of etching a selected portion of the first insulating layer to form a contact hole and filling the contact hole with a conductive material. A second insulating layer composed of PE-TEOS(plasma enhanced tetraethylorthosilicate) oxide is formed on the first oxide layer to a thickness of desired height of the storage node.
A cylindrical opening is formed in the second insulating layer. To obtain process margins, optional etching stopper nitride layer may be formed between two insulating layers. A first conductive material as for a storage node is deposited in the opening and on the second insulating layer. HSG silicons are formed on the first conductive layer. An HSG silicons. Protection layer is then formed. The protection layer is made of a nitride layer to a thickness of about at least 5 angstroms sufficient to protect HSG silicons during cleaning process. A Planarization layer composed of USG(undoped silicate glass) is deposited on the second insulating layer to completely fill the cylindrical opening. This Planarization layer serves to protect the contamination and defects of the interior cylinder. Planarization process is carried out on the Planarization layer down to a top surface of the second insulating layer.
Remainder of the planarization layer in the cylindrical opening is then selectively removed by chemical solution such as LAL to form a storage node. During this cleaning process, the HSG silicon is protected from the wet chemical due to the presence of the protection nitride layer. A second nitride layer as for a dielectric film is then formed on the storage node. Through oxidation process, an oxide layer is formed on the second nitride layer to complete dielectric layer of nitride/oxide. A second conductive layer as for a plate node is then deposited on the dielectric layer to form a cylindrical capacitor.
Resulting capacitor from the above-mentioned method is composed of a cylindrical storage node having HSG silicons on interior thereof, a dielectric film and a plate node. The dielectric film is made of nitride/oxide structure. More specifically, nitride/oxide structure is made of a protection nitride/second nitride/oxide at the interior storage node. On the other hand, nitride/oxide structure is made of second nitride/oxide at the exterior storage node. Bottom of the storage node is electrically connected to the top surface of the contact plug.
In above method, the second oxide layer outside of the storage node can be removed.
In another aspect of the present invention, nitride layer for undercutting formation can be formed on the first insulating layer. In this case the contact plug is formed in the nitride layer and the first insulating layer. More specifically, after depositing the first insulating layer on the integrated circuit substrate, the nitride layer is deposited thereon. Selected portion of the nitride layer and first insulating layer is etched to form a contact hole and then filled with a conductive material to form the contact plug. A second insulating layer is formed and a cylindrical opening is formed therein to the contact plug. A first conductive material is deposited in the opening and on the second insulating layer.
HSG silicons are formed on the first conductive layer and HSG silicon protection layer composed of nitride is formed. A Planarization layer is deposited on the second insulating layer to completely fill the cylindrical opening. Planarization process is carried out down to a top surface of the second insulating layer to form a storage node.
Remainder of the planarization layer in the cylindrical opening and the second insulating layer outside the storage node are removed by wet chemical using the nitride layer for undercutting as an etching stopper. The nitride layer is then selectively removed to cause the undercutting formation below the storage node and thus further increasing the surface area thereof.
Subsequently, nitride layer as for a dielectric is formed on the resulting structure and an oxide layer is then formed through oxidation process and thereby completing dielectric layer of nitride/oxide structure.
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Shin Hyun-bo
Yu Young-Sub
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Smith Matthew
Yevsikov V.
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