Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-09-27
1999-04-13
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438586, 438589, H01L 218236, H01L 2128
Patent
active
058937366
ABSTRACT:
An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased. In contrast to those JFET regions in the prior art which are formed by performing a high dose implant and/or high dose diffusion of first conductivity type dopants, the devices according to the present invention reduce the adverse influences on threshold voltage caused by high dose implants of ions adjacent the periphery of the base regions.
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B. Jayant Baliga, Power MOSFET, Chapter 7, Power Semiconductor Devices, Jan. 1996, pp. 367-372.
Daisuke Ueda et al., Deep-Trench Power MOSFET With An Ron Area Product Of 160 m.OMEGA. mm.sup.2, IEDM, 28.2, 1986, pp. 638-641., Dec. 1986.
Kim Soo-seong
Lee Sang-yong
Lebentritt Michael S.
Niebling John F.
Samsung Electronics Co,. Ltd.
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