Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-09
2002-12-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S199000
Reexamination Certificate
active
06495422
ABSTRACT:
FIELD OF THE INVENTION
“The present invention relates generally to semiconductor fabrication and more specifically to methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application.”
BACKGROUND OF THE INVENTION
For deep sub-micron complimentary metal oxide semiconductor (CMOS) technology, gate oxides have been scaled down aggressively toward direct tunneling region. For ultra-thin SiO
2
gate oxide, leakage current will increase tremendously as gate oxide thicknesses are reduced. This will cause large standby power consumption thus making such products commercially unacceptable.
To solve this issue, different high dielectric constant (high-k) materials have been proposed to replace SiO
2
as the gate oxide because of leakage current reduction ability.
U.S. Pat. No. 6,184,072 B1 to Kaushik et al. describes various silicon oxynitride (or oxide) and metal oxide high-k gate dielectric layers.
U.S. Pat. No. 6,100,120 to Yu describes a metal oxide dielectric layer and process.
U.S. Pat. No. 5,639,316 to Cabral, Jr. et al. describes a method of protecting a refractory metal from oxidation during high temperature annealing.
U.S. Pat. No. 6,027,977 to Mogami describes a method of fabricating a semiconductor device with a metal insulator semiconductor (MIS) structure.
U.S. Pat. No. 5,960,289 to Tsui et al. describes a method for making a dual-thickness gate oxide layer using a nitride/oxide composite region.
U.S. Pat. No. 6,204,203 B1 to Narwankar et al. describes a method of forming a metal oxide dielectric film.
U.S. Pat. No. 6,114,258 to Miner et al. describes a method of oxidizing a substrate in the presence of nitride and oxynitride films.
The article entitled “Device and Reliability of High-K Al
2
O
3
Gate Dielectric with Good Mobility and Low D
it
”, 1999 Symposium on VLSI Technology Digest of Technical Papers, pages 135 and 136, describes a process to fabricate Al
2
3
gate dielectric having a dielectric constant k of form 9.0 to 9.8 that is greater than the dielectric constant of Si
3
N
4
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of forming high-k gate dielectrics and gate oxides.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having isolation regions which separate the structure into at least one core device active region and one I/O active region is provided. A buffer layer is formed over the structure and the isolation regions. A metal containing layer is formed over the buffer layer. The metal containing layer and the buffer layer are patterned to: form an exposed patterned metal containing layer within the at least one core device action region ; and expose the structure within the at least one I/O active region. The exposed patterned metal containing layer and the exposed structure within the at least one I/O active region are oxidized to simultaneously form: the high-k metal oxide dielectric layer within the at least one core device active region; and the gate oxide dielectric layer within the at least one I/O active region.
REFERENCES:
patent: 5639316 (1997-06-01), Cabral, Jr. et al.
patent: 5960289 (1999-09-01), Tsui et al.
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6027977 (2000-02-01), Mogami
patent: 6100120 (2000-08-01), Yu
patent: 6114258 (2000-09-01), Miner et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6204203 (2001-03-01), Narwankar et al.
patent: 6228721 (2001-05-01), Yu
patent: 6255698 (2001-07-01), Gardner et al.
“Device and Reliability of High-K A12O3Gate Dielectric with Good Mobility and Low Dit”, by Chin et al., 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 135-136.
Chen Shih-Chang
Yu Mo-Chiun
Ackerman Stephen B.
Lindsay Jr. Walter L.
Niebling John F.
Saile George O.
Stanton Stephen G.
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