Methods of forming ferroelectric random access memory...

Details Methods of forming ferroelectric random access memory... Methods of forming ferroelectric random access memory...

1998-10-06

2001-05-22

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C257S300000, C257S310000, C257S311000

Reexamination Certificate

active

06235573

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit device fabrication methods, and more particularly to methods of fabricating integrated circuit memory devices and memory devices formed thereby.
BACKGROUND OF THE INVENTION
Ferroelectric random access memory (FRAM) devices are “nonvolatile” memory devices because they preserve data stored therein even in the absence of a power supply signal. The nonvolatile nature of a ferroelectric memory cell is a direct consequence of using a ferroelectric material as the dielectric of the cell's capacitor. Typical ferroelectric materials which can be used for the ferroelectric capacitor include Phase III potassium nitrate, bismuth titanate and lead zirconate titanate Pb(Zr, Ti)O
3
(PZT). Because these ferroelectric materials possess hysteresis characteristics, the polarity (i.e., state) of the ferroelectric material can be maintained even after interruption of the power supply. Thus, data (e.g., logic 0,1) can be stored in the FRAM as the polarity state of the ferroelectric material in each capacitor.
FRAM devices may typically be classified into two categories. In the first category, the gate insulating film of a field effect transistor comprises a ferroelectric material. In the second category, a field effect access transistor and a ferroelectric capacitor are provided as part of a unit cell. Unfortunately, the electrical characteristics of FRAM devices from the first category may suffer if the lattice constants or thermal expansion coefficients between a silicon substrate and the ferroelectric gate insulating film are significantly different. However, FRAM devices in the second category typically do not suffer from such limitations on performance.
Referring now to
FIG. 1
, a typical FRAM device from the second category includes a field effect access transistor having a gate G, source S and drain D which are electrically coupled to a word line W/L, second electrode of a ferroelectric capacitor C
F
and a bit line B/L, respectively. A plate line P/L is also electrically connected to a first electrode of the ferroelectric capacitor C
F
. As illustrated by
FIG. 2
, the conventional FRAM device of
FIG. 1
includes a source region
9
and a drain region
11
which are formed in a semiconductor substrate
1
of first conductivity type (e.g., P-type). A field oxide isolation region
3
is also provided in the substrate
1
. The access transistor also includes a gate oxide layer
5
and a gate electrode
7
which is electrically coupled in common to other gate electrodes as a word line W/L. First and second borophosphosilicate glass (BPSG) layers
13
and
19
are also provided. A bit line
23
is also provided. The bit line
23
extends through the first and second BPSG layers, as illustrated. An upper electrode
21
of the ferroelectric capacitor is electrically connected to the source region
9
. The lower electrode
15
and ferroelectric dielectric layer IS of the ferroelectric capacitor are provided on the first BPSG layer
13
. The lower electrode and upper electrode of the ferroelectric capacitor may comprise platinum and the ferroelectric dielectric layer may comprise PZT.
Notwithstanding the above-described nonvolatile integrated circuit memory devices, there continues to be a need for more highly integrated nonvolatile memory devices (e.g., FRAM devices) and methods of forming these memory devices using simplified and economical fabrication techniques.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming nonvolatile integrated circuit memory devices.
It is another object of the present invention to provide improved methods of forming ferroelectric random access memory (FRAM) devices.
It is still another object of the present invention to provide methods of forming highly integrated ferroelectric random access memory (FRAM) devices having preferred electrical characteristics.
These and other objects, advantages and features of the present invention are provided by methods of forming ferroelectric random access memory devices which comprise the steps of forming first and second field effect access transistors in a semiconductor substrate, forming first and second bit lines (BL) which are electrically coupled to a drain region of the first field effect access transistor and a drain region of the second field effect access transistor, respectively, and forming first and second ferroelectric capacitors (C
F
) which extend between the first and second bit lines in order to improve integration density. These first and second ferroelectric capacitors also share a first electrode (extending between the first and second bit lines) and have respective second electrodes electrically coupled to respective source regions of the first and second field effect access transistors.
The preferred methods may also include the step of forming a field oxide isolation region adjacent a face of the substrate and extending between the first and second field effect access transistors. This field oxide isolation region may define an inactive portion of the substrate. In addition, a step may be provided to form a first interlayer dielectric layer on the first and second field effect access transistors and on the field oxide isolation region. The step of forming the first and second ferroelectric capacitors may also comprise the preferred steps of forming a first conductive layer on the first interlayer dielectric layer, forming a ferroelectric dielectric layer (e.g., PZT, PLZT) on the first conductive layer, forming a second conductive layer on the ferroelectric dielectric layer, patterning the second conductive layer and the ferroelectric dielectric layer (using a first mask) to define the second electrodes of the first and second ferroelectric capacitors and then patterning the first conductive layer (using a second mask) to define the first electrode which is shared by the first and second ferroelectric capacitors. The step of forming a first conductive layer is preferably preceded by the step of forming a barrier layer comprising titanium dioxide on the first interlayer dielectric layer. This barrier layer is designed to improve the degree of adhesion between the first conductive layer and the field oxide isolation region. The first and second conductive layers may also comprise a material selected from the group consisting of Pt, ReO
2
, RuO
2
and MoO
3
and combinations thereof.
The step of patterning the first conductive layer may then be followed by the step of encapsulating the second electrodes with a titanium dioxide (TiO
2
) capping layer. The preferred methods may also comprise the steps of forming a second interlayer dielectric layer on the capping layer and on the first interlayer dielectric layer and then patterning the first and second interlayer dielectric layers and capping layer to expose the source and drain regions of the first and second field effect access transistors and expose the second electrodes of the first and second ferroelectric capacitors.


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