Methods of forming EEPROM memory cells having uniformly thick tu

Details Methods of forming EEPROM memory cells having uniformly thick tu Methods of forming EEPROM memory cells having uniformly thick tu

1996-12-24

1999-03-30

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438450, 438452, H01L 218247

Patent

active

058888713

ABSTRACT:
Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunnelling oxide layer, a silicon nitride layer is preferably patterned on the tunnelling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunnelling oxide layer and channel region to complete the memory cell.

REFERENCES:
patent: 5110756 (1992-05-01), Gregor et al.
patent: 5147813 (1992-09-01), Woo
patent: 5286666 (1994-02-01), Katto et al.
patent: 5521109 (1996-05-01), Hsue et al.
patent: 5663080 (1997-09-01), Cereda et al.

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