Methods of forming different gate structures in NMOS and...

Details Methods of forming different gate structures in NMOS and... Methods of forming different gate structures in NMOS and...

2008-07-15

2008-07-15

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S197000, C257SE21130, C257SE21200, C257SE21203

Reexamination Certificate

active

07399670

ABSTRACT:
A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

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Korean Office Action for Korean Application No. 10-2004-0062640; dated Jan. 19, 2006.

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