Methods of forming capacitor electrodes having reduced susceptib

Details Methods of forming capacitor electrodes having reduced susceptib Methods of forming capacitor electrodes having reduced susceptib

1997-11-13

2000-10-10

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

061301248

ABSTRACT:
Methods of forming capacitors in memory devices include the steps of forming a first electrically insulating layer having a first conductive contact plug therein, on a semiconductor substrate, and then forming a first diffusion barrier pattern in electrical contact with the first conductive contact plug. A second electrically insulating layer having a contact hole therein is then formed on an upper surface of the first diffusion barrier pattern, to inhibit parasitic oxidation of the first diffusion barrier pattern. A lower electrode of a capacitor is then formed on the second electrically insulating layer. The lower electrode is electrically coupled to the first diffusion barrier pattern and may contact the first diffusion barrier pattern directly or may be coupled through a second diffusion barrier pattern to the first diffusion barrier pattern. A dielectric layer and upper electrode are then formed on the lower electrode. The step of forming the first electrode may comprise patterning a conductive layer to extend on an upper surface of second electrically insulating layer and into the contact hole so that the first electrode has a relatively greater cross-sectional thickness in the contact hole to inhibit migration of oxidation to the first diffusion barrier pattern. The step of forming a first electrode may also be preceded by the step of forming a second diffusion barrier pattern in the contact hole. The second diffusion barrier pattern also preferably inhibits migration of oxidation to the first diffusion barrier pattern during processing.

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