Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-25
2008-10-28
Jackson, Jerome (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C257SE21135, C257S335000
Reexamination Certificate
active
07442613
ABSTRACT:
A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
REFERENCES:
patent: 6078079 (2000-06-01), Ogoh
patent: 6255174 (2001-07-01), Yu
patent: 6274489 (2001-08-01), Ono et al.
patent: 6570233 (2003-05-01), Matsumura
patent: 6858529 (2005-02-01), Chung et al.
patent: 2004/0152297 (2004-08-01), Ooto et al.
patent: 2005/0064689 (2005-03-01), Mouli
Hur Ki-Jae
Oh Kyung-Seok
Park Joo-Sung
Shin Jung-Hyun
Budd Paul A
Choi Monica H.
Jackson Jerome
Samsung Electronics Co,. Ltd.
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