Methods of forming a conductive layer structure and methods...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S330000, C257S332000

Reexamination Certificate

active

08067285

ABSTRACT:
In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

REFERENCES:
patent: 6984575 (2006-01-01), Yamamoto
patent: 7154144 (2006-12-01), Kim et al.
patent: 2005/0020086 (2005-01-01), Kim et al.
patent: 2006/0244055 (2006-11-01), Jang et al.
patent: 2007/0099384 (2007-05-01), Han et al.
patent: 2007/0148876 (2007-06-01), Yu
patent: 2008/0032512 (2008-02-01), Kim et al.
patent: 2008/0128800 (2008-06-01), Song et al.
patent: 2009/0163010 (2009-06-01), Oh et al.
patent: 10 2005-0011376 (2005-01-01), None
patent: 10 2008-0003055 (2008-01-01), None
patent: 10 2008-0077856 (2008-08-01), None

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