Methods of fabricating vertical twin-channel transistors

Details Methods of fabricating vertical twin-channel transistors Methods of fabricating vertical twin-channel transistors

2011-03-01

2011-03-01

Louie, Wai-Sing (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S157000, C438S154000

Reexamination Certificate

active

07897463

ABSTRACT:
A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

REFERENCES:
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 5308782 (1994-05-01), Mazure et al.
patent: H1435 (1995-05-01), Cherne et al.
patent: 6137122 (2000-10-01), Liaw et al.
patent: 6500710 (2002-12-01), Nakagawa
patent: 6504755 (2003-01-01), Katayama et al.
patent: 7259048 (2007-08-01), Chaudhry et al.
patent: 7351622 (2008-04-01), Buh et al.
patent: 7491608 (2009-02-01), Forbes
patent: 2006/0157683 (2006-07-01), Scheuerlein
Notice of Reasons for Refusal for corresponding Korean application No. 2006-74202; Jun. 25, 2007.
English translation of Notice of Reasons for Refusal for corresponding Korean application No. 2006-74202; Jun. 25, 2007.

Affiliated with

Also associated with

Rating

Methods of fabricating vertical twin-channel transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of fabricating vertical twin-channel transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabricating vertical twin-channel transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2688046