Methods of fabricating semiconductor devices with scalable...

Details Methods of fabricating semiconductor devices with scalable... Methods of fabricating semiconductor devices with scalable...

2006-09-26

2006-09-26

Ho, Tu-Tu (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000, C257S319000, C257S321000

Reexamination Certificate

active

07112492

ABSTRACT:
Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

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Notice to File a Response/Amendment to the Examination Report for Korean patent application No. 10-2003-0031302 mailed on May 30, 2005.

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