Methods of fabricating semiconductor devices including...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S238000, C438S585000, C438S672000, C438S700000, C438S740000, C438S778000, C438S970000, C438S384000, C257S288000, C257S350000, C257S358000, C257S360000, C257S379000, C257S380000, C257S635000, C257S637000

Reexamination Certificate

active

11011644

ABSTRACT:
Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.

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patent: 10-2004-0016679 (2004-02-01), None
Ichige et al., “A Novel Self-Aligned Shallow Trench Isolation Cell for 90nm 4Gbit NAND Flash EEPROMs,”2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 89-90.
Korean Intellectual Office, “Notice to File a Response/Amendment to the Examination Report” corresponding to Korean Patent Application No. 10-2004-0037463, mailed Dec. 21, 2005.

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