Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-22
2009-02-10
Nguyen, Thanh (Department: 2893)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S267000, C438S261000
Reexamination Certificate
active
07488648
ABSTRACT:
A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.
REFERENCES:
patent: 6475857 (2002-11-01), Kim et al.
patent: 2003/0067024 (2003-04-01), Kim et al.
patent: 2004/0238974 (2004-12-01), Baik
patent: 62-274775 (1987-11-01), None
patent: 2001-250950 (2001-09-01), None
patent: 2003-067021 (2003-04-01), None
patent: 2002-0096809 (2002-12-01), None
patent: 1020030013586 (2003-02-01), None
“Design of 10-nm Scale Recessed Asymmetric Schottky Barrier Mosfets” Earliest publication date unknown but for examination purposes it is believed to be before filing date of this application. 9 sheets.
Wang et al; “Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors” Applied Physics Letters, vol. 74, No. 8, Feb. 22, 1999, pp. 1174-1176.
Notice to Submit Response corresponding to Korean Patent Application No. 10-2004-0046962 mailed Jan. 27, 2006.
Myers Bigel & Sibley Sajovec, PA
Nguyen Thanh
Samsung Electronics Co,. Ltd.
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