Methods of fabricating read only memory devices including...

Details Methods of fabricating read only memory devices including... Methods of fabricating read only memory devices including...

2002-02-28

2004-04-06

Mai, Son (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06716704

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-35701, filed Jun. 22, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods, and more particularly Read Only Memory (ROM) devices and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Integrated circuit Read Only Memory (ROM) devices are widely used for storing programs and/or data in a nonvolatile manner. Once data is programmed into a ROM device, it remains permanently in the ROM device and can be read but generally cannot be overwritten. As is well known to those having skill in the art, a ROM generally includes a transistor array in a cell region, wherein individual transistors are programmed to store a one or a zero using well known techniques. Supporting circuitry, such as address decoders and/or controllers also may be included in a peripheral region of the ROM.
As ROM devices become more highly integrated, the number of transistors per unit area may increase, and the linewidths may be reduced. This increase in density and/or decrease in linewidth may undesirably increase resistance and/or parasitic capacitance, and may also undesirably decrease the reliability and/or yield of the devices.
FIG. 1
is a plan view of a cell region of a conventional ROM.
FIGS. 2
,
3
,
4
and
5
are cross-sectional views which may be obtained by cutting the cell region of
FIG. 1
along lines of I—I, II—II, III—III and IV—IV, respectively.
Referring to
FIGS. 1-5
, the entire cell region is an active region. That is, no isolation layer is formed in the cell region. High concentration N-type doping layers
20
buried in a substrate are formed as parallel lines. The surface of the substrate is covered with an insulating layer. The insulating layer includes a gate insulation layer and/or a thick insulation layer
60
on the buried high concentration N-type doping layer
20
that insulates a gate line
10
from the buried doping layer
20
. The gate lines
10
are parallel lines which cross the buried doping layers
20
. A first polysilicon layer pattern
50
is provided on the gate insulation layer and at a lattice region where each of the gate lines
10
crosses the parallel lines, each of which lies between the buried high concentration N-type doping layers
20
. The first polysilicon layer pattern
50
provides a gate electrode at the lattice region, together with a second polysilicon layer of the gate line
10
. At regions outside of the gate electrodes, the gate line
10
is composed of the second polysilicon layer. At some of the gate electrodes covered by the first polysilicon layer pattern
50
, indicated by the reference number
40
of
FIG. 1
, a channel layer ion implantation is performed through a pattern mask. The ROM is programmed according to the ion implantation.
A Plasma Enhanced Chemical Vapor Deposition (PECVD) oxide layer
70
is stacked over the gate line
10
, and a Boro-Phospo-Silicate-Glass (BPSG) layer
80
is stacked thereon to form a planarized interlayer insulation layer. A metal interconnection
30
is formed on the planarized interlayer insulation layer. In
FIGS. 1-5
, the metal interconnection
30
is formed once per two line patterns in parallel with the line patterns of the buried high-concentration N-type doping layer
20
and over the line patterns. A protective layer
90
is formed over the metal interconnection
30
. The metal interconnection
30
provides a main bit line and is connected with the buried high concentration N-type doping layer
20
, which is a sub-bit line below the metal interconnection
30
, at a periphery of a selected cell transistor.
In order to select a certain memory cell, non-zero voltages may be applied on the gate line
10
passing the selected cell transistor, and on the main bit line connected with the buried high concentration N-type doping layer
20
comprising a drain region of the selected cell transistor. As a result, the voltage of the buried high concentration N-type doping layer
20
composing a source region becomes 0 V. If a threshold voltage applied on a channel region of a gate electrode bottom of the selected cell transistor is programmed to be higher than a voltage applied on the gate line
10
, the cell transistor enters an “off” state and the bit line is not discharged, so that the cell transistor is read as “off”. Conversely, if the threshold voltage applied on the channel region of the selected cell transistor is programmed to be lower than the voltage applied on the gate line
10
, the cell transistor enters an “on” state and the bit line is discharged, so that the cell transistor is read as “on”. The design, fabrication and operation of conventional ROM devices are well known to those having skill in the art and need not be described further herein.
FIGS. 6-9
are cross-sectional views of a first polysilicon layer along the gate line in a conventional ROM device, during intermediate fabrication steps.
Referring to
FIG. 6
, a gate insulation layer
110
of about 100 Å in thickness is formed on an integrated circuit substrate, such as a silicon semiconductor substrate
100
. A first polysilicon layer
120
is stacked in a thickness of about 200 Å to about 1000 Å. A capping layer
130
is formed of a silicon nitride layer, and an antireflection layer
140
is formed of a silicon oxynitride layer thereon. The resultant structure is patterned to form a line pattern composed of the antireflection layer
140
, the capping layer
130
, and the first polysilicon layer
120
. During patterning, a partial thickness of the gate insulation layer
110
outside the line pattern is removed by over-etching.
Referring to
FIG. 7
, a silicon nitride layer is conformally stacked over the line pattern in a thickness of about 100 Å to about 500 Å and removed by anisotropic etching to form a sidewall spacer
160
at the sidewall of the line pattern composed of the first polysilicon layer
120
and the capping layer
130
. As a partial thickness of the spacer
160
is removed by over-etching, the gate insulation layer covering the antireflection layer and the substrate also is removed. N-type ions are implanted into the substrate in a dose amount of about 10
15
ions/cm
2
. Low ion implantation energy below 30 KeV is applied at the substrate surface to form a high concentration N-type doping layer
150
between the patterns including the first polysilicon layer
120
.
Referring to
FIG. 8
, the substrate is thermally oxidized to form a thermal oxide layer
170
on the substrate
100
, except the pattern covered with the capping layer
130
. The surface of the substrate
100
is rapidly oxidized in thermal oxidation due to the earlier ion implantation, thereby volumetrically expanding. Thus, the thermal oxide layer
170
is thicker than the gate insulation layer
111
under the first polysilicon layer
120
of the pattern. The ion-implanted dopants are moved downward by the thermal oxide layer
170
, to form a buried high concentration N-type doping layer
151
. The first polysilicon layer
120
is covered with the capping layer
130
and the spacer
160
, thereby not being oxidized.
Referring to
FIG. 9
, the spacer
160
and the capping layer
130
covering the first polysilicon layer
120
are removed by wet etching, and a second polysilicon layer
180
is stacked. The first polysilicon layer
120
and the second polysilicon layer
180
are patterned to form a gate line including a gate electrode. Subsequent processes are performed similar to a conventional CMOS process, and are well known to those skilled in the art. Accordingly, additional fabrication details need not be described further herein.
According to a conventional method of fabricating a ROM, the reliability of the gate insulation layer may be degraded. In particular, the gate insulation layer exists at a region V of
FIG. 9
, where the spacer was between the thermal oxid

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