Methods of fabricating MOS transistors having recesses with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257SE21619, C257SE21634

Reexamination Certificate

active

08039350

ABSTRACT:
Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

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patent: 10-0332108 (2002-04-01), None
English translation on Dec. 2007 of JP 2002151682 A, published on May 5, 2002.

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