Methods of fabricating integrated circuit transistors by...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S780000, C438S793000, C438S794000, C438S149000, C257SE21041, C257SE21049, C257SE21005

Reexamination Certificate

active

07541234

ABSTRACT:
Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

REFERENCES:
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 5024959 (1991-06-01), Pfiester
patent: 5439834 (1995-08-01), Chen
patent: 5460998 (1995-10-01), Liu
patent: 5620919 (1997-04-01), Godinho et al.
patent: 5766991 (1998-06-01), Chen
patent: 5936300 (1999-08-01), Sasada et al.
patent: 6359276 (2002-03-01), Tu
patent: 6475888 (2002-11-01), Sohn
patent: 6573172 (2003-06-01), En et al.
patent: 7022561 (2006-04-01), Huang et al.
patent: 7115954 (2006-10-01), Shimizu et al.
patent: 7190033 (2007-03-01), Chang et al.
patent: 7193254 (2007-03-01), Chan et al.
patent: 7211869 (2007-05-01), Chan et al.
patent: 7214629 (2007-05-01), Luo et al.
patent: 7220630 (2007-05-01), Cheng et al.
patent: 7244644 (2007-07-01), Zhu et al.
patent: 7288451 (2007-10-01), Zhu et al.
patent: 7309637 (2007-12-01), Lee et al.
patent: 7314836 (2008-01-01), Golonzka et al.
patent: 7374987 (2008-05-01), Chidambarrao et al.
patent: 2001/0001718 (2001-05-01), Kikushima et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2004/0180483 (2004-09-01), Park et al.
patent: 2004/0180504 (2004-09-01), Lee et al.
patent: 2005/0020022 (2005-01-01), Grudowski
patent: 2005/0069816 (2005-03-01), Jung et al.
patent: 2005/0194596 (2005-09-01), Chan et al.
patent: 2005/0214998 (2005-09-01), Chen et al.
patent: 2005/0230756 (2005-10-01), Chang et al.
patent: 2006/0128086 (2006-06-01), Chidambarrao et al.
patent: 2006/0228848 (2006-10-01), Chan et al.
patent: 2007/0048907 (2007-03-01), Lee et al.
patent: 2007/0077708 (2007-04-01), Frohberg et al.
patent: 10-256390 (1998-09-01), None
patent: 2003-60076 (2003-02-01), None
patent: 2004-282068 (2004-10-01), None
patent: 1995-0011781 (1995-10-01), None
patent: 10-0247478 (2000-03-01), None
patent: 2002-0054898 (2002-07-01), None
patent: 10-2004-0057519 (2004-07-01), None
patent: 10-2004-0079747 (2004-09-01), None
patent: 10-2004-0080510 (2004-09-01), None
patent: 10-2004-0102656 (2004-12-01), None
Notice of Allowance, KR 10-2006-0099917, Nov. 29, 2007.
JSR Micro Materials Innovation, “Tarc Resists”, downloaded on Sep. 17, 2005 from http://www.jsrmicro.com/pro—photo—Tarc.html.

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