Methods of fabricating integrated circuit memory devices

Details Methods of fabricating integrated circuit memory devices Methods of fabricating integrated circuit memory devices

2002-03-19

2004-03-23

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000

Reexamination Certificate

active

06709915

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-30772, filed on Jun. 1, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to an integrated circuit memory device and a method of fabricating the same, and more particularly, to an integrated circuit memory device which is capable of enhancing the capacitance of a capacitor without increasing the height of the capacitor and a method of fabricating the same.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuit devices, increases, the area occupied by a unit cell continues to decrease. Since the driving capability of integrated circuit devices, such as dynamic random access memories (DRAM), is strongly dependent on the capacitance of a capacitor, a variety of attempts for increasing the capacitance of a capacitor have been carried out, irrespective of the decrease of the area occupied by the capacitor. Accordingly, in order to increase the capacitance of a capacitor by increasing the effective area of the capacitor, capacitors have been formed to have a three-dimensional structure, such as a concave shape, a cylinder shape, a fin shape, or a box shape.
Hereinafter, a method of fabricating a conventional integrated circuit memory device including a concave-shaped storage node electrode will be described with reference to
FIGS. 1A through 1C
. In
FIGS. 1A through 1C
, the drawings indicated by “X direction” are cross-sectional views of a semiconductor substrate taken along a direction parallel to word lines, and the drawings indicated by “Y direction” are cross-sectional views of a semiconductor substrate taken along a direction parallel to bit lines.
Referring to
FIG. 1A
, word line structures
15
are formed on a semiconductor substrate
10
, on which an isolation layer
11
is formed, by a well-known method. Here, each of the word line structures
15
includes a gate insulating layer
12
, a gate electrode
13
on the gate insulating layer
12
, and an insulating material
14
covering the top surface and sides of the gate electrode
13
. Contact plugs
16
are formed on the semiconductor substrate
10
between the word line structures
15
in a self-aligned manner, and then a first interlayer insulating layer
17
is formed on the semiconductor substrate
10
on which the contact plugs
16
are formed.
Next, a second interlayer insulating layer
18
is formed on the contact plugs
16
and the first interlayer insulating layer
17
, and then is selectively etched to expose some of the contact plugs
16
. Next, bit line structures
21
are formed on the second interlayer insulating layer
18
, in contact with the exposed contact plugs. Here, each of the bit line structures
21
includes a bit line
19
and an insulating material
20
covering the top surface and sides of the bit line
19
. A third interlayer insulating layer
22
and an etch stopper
23
are sequentially formed on the semiconductor substrate
10
on which the bit line structures
21
are formed.
Referring to
FIG. 1B
, predetermined portions of the etch stopper
23
and the third interlayer insulating layer
22
are etched to expose selected portions of the contact plugs
16
, thereby forming storage node contact holes
24
. Next, storage node contact plugs
25
are formed in the storage node contact holes
24
by a well-known method.
Next, as shown in
FIG. 1C
, storage node electrodes
26
are formed to be in contact with exposed storage node contact plugs
25
by a well-known method. A dielectric layer
27
is deposited along the surfaces of the storage node electrodes
26
, and then a plate electrode
28
is formed on the semiconductor substrate
10
on which the dielectric layer
27
is formed.
However, the conventional integrated circuit memory device has the following problems. Firstly, as the integration density of integrated circuit memory devices increases, the pitch size of interconnections typically decreases proportionally. If the pitch size of interconnections is reduced to 0.21 &mgr;m or less, a capacitance no less than 20 fF per a unit cell is desirable. In order to obtain capacitance having such a value, it is desirable that the height of each storage node electrode be no less than 10,000 Å.
However, if the height of storage node electrodes is increased in order to obtain a high capacitance, the aspect ratio of a cell region can considerably increase, causing a great step difference between the cell region at which the storage node electrodes will be formed and a peripheral region at which other circuit devices will be formed. In addition, if even a slight physical impact is applied to the storage node electrodes, the storage node electrodes (capacitors) may be tilted to one side or may be broken, and thus multi-bit or twin-bit failure occurring when the upper parts of adjacent capacitors are contacted with each other may be caused.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention, an integrated circuit memory device includes a plurality of word line structures formed on a semiconductor substrate. Contact plugs are disposed between adjacent word line structures. Bit line structures are formed to be in electrical contact with predetermined contact plugs selected among the contact plugs. An interlayer insulating layer insulates the contact plugs from one another and insulates non-selected contact plugs from the bit line structures. Storage node contact plugs are formed to be in electrical contact with the non-selected contact plugs. Storage node electrodes are formed on the storage node contact plugs. A dielectric layer is deposited on the surfaces of the storage node contact plugs and the storage node electrodes. A plate electrode is formed on the surface of the dielectric layer and extends between the storage node contact plugs, and more preferably between lower portions of the storage node contact plugs. The surface area of the interface between the plate electrode and the combination of storage node contact plugs and storage node electrodes is increased by having the plate electrode extending between the storage note contact plugs. For a capacitor formed in this fashion the increased surface area can provide increased capacitance while avoiding increasing the size of the capacitor. The lower portions of the storage node contact plugs are fit into spaces between the bit line structures so as to be supported by the bit line structures.
The word line structures each include a gate electrode, a gate insulating layer insulating the gate electrode from the semiconductor substrate, and an insulating material covering the top surface and sides of the gate electrode, and the bit line structures each include a bit line and an insulating layer covering the top surface and sides of the bit line.
According to a second aspect of the present invention, there is provided a method for manufacturing an integrated circuit memory device. A plurality of word line structures are formed on predetermined portions of a semiconductor substrate on which an active region is defined. Contact plugs are formed between the word line structures on the active region. An insulating layer is formed on the semiconductor substrate on which the contact plugs are formed. Bit line structures are formed on the insulating layer so as to be in electrical contact with predetermined contact plugs selected from among the contact plugs. An interlayer insulating layer is deposited on the bit line structures. An etch stopper is formed on the interlayer insulating layer. Storage node contact holes are formed by etching predetermined portions of the interlayer insulating layer and the etch stopper to expose non-selected contact plugs. Storage node contact plugs are formed to in the storage node contact holes. Storage node electrodes are formed to be in electrical contact with the storage node contact plugs. The remaining etch stopper is removed to expose surfaces on upper portions of the storage node

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