Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-30
2002-04-09
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S763000
Reexamination Certificate
active
06368909
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods therefor, and more particularly to integrated circuit ferroelectric capacitors and methods of fabricating same.
BACKGROUND OF THE INVENTION
Integrated circuit capacitors are widely used in integrated circuits, such as Random Access Memory (RAM) devices including Dynamic Random Access Memory (DRAM) devices. For example, in a single transistor DRAM memory cell, the charge stored in a memory cell capacitor is selectively coupled to a memory bit line through the source/drain path of an access transistor. The gate electrode of the access transistor is coupled to a word line. This charge is sensed in order to determine the state of the memory cell. Since the charge on the capacitor tends to dissipate, DRAM cells are refreshed periodically in order to preserve the data contents thereof.
Ferroelectric materials have been used as the dielectric in a memory cell capacitor. Ferroelectric materials can exhibit a high dielectric constant. Moreover, RAM devices that use ferroelectric capacitors for memory cells, often referred to as Ferroelectric RAMs or FRAMs, also can be non-volatile because the ferroelectric material has two stable polarization states that can be defined by a hysteresis loop of polarization versus applied voltage. By measuring the charge which flows when a voltage is applied to a ferroelectric capacitor, the polarization state of the ferroelectric material can be determined. One polarization state is assigned a logic level “zero” and the other polarization state is assigned a logic level “one”. Thus, ferroelectric capacitors can be used to store binary data in a RAM without the need to refresh the data.
FIG. 1
is a conventional hysteresis loop describing polarization charges (P:&mgr;C/cm
2
) in a ferroelectric capacitor as a function of voltage (V) across the ferroelectric capacitor. It should be noted that when the voltage across the ferroelectric capacitor is zero, the ferroelectric capacitor can be in either of two polarization states, a logic “one” polarization state or a logic “zero” polarization state.
In
FIG. 1
, when the voltage across the capacitor is zero, the ferroelectric capacitor is, for example, at logic “zero” polarization state, for example “−Qr” as indicated by “D”. When the voltage across the ferroelectric capacitor increases, toward the +V direction, the polarization charge (−Qr) increases toward the +P direction. As a result, if the voltage across the ferroelectric capacitor increases up to the voltage “+Vs”, the polarization charge reaches a saturation state of maximum value “+Qs” as indicated at “A”. After the polarization charge reaches the saturation state “A”, even though the voltage decreases toward zero, the polarization charge does not drop to zero but stays at the “B” stage of remnant polarization state “+Qr”, i.e., a logic “one” polarization state. On the other hand, when the voltage across the ferroelectric capacitor decreases from zero in the −V direction, i.e., opposite the initial direction, the polarization charge decreases in the −P direction from “+Qr”. As a result, if the voltage decreases to “−Vs”, the polarization charge reaches the saturation state “C” of minimum value “−Qs”. After the polarization charge reaches the saturation state “C”, even though the voltage increases toward zero, the polarization charge does not drop to zero but stays at the “D” stage of remnant polarization state “−Qr”, i.e., logic “one” polarization state.
Thus, when a positive or negative voltage is applied across the ferroelectric capacitor and removed, a remnant polarization “−Qr” or “+Qr” will be present in the ferroelectric material. Subsequently, when a voltage pulse of opposite polarity is applied across the capacitor, the remnant polarization is reversed. It is thus possible to switch repeatedly between two stable polarization states by means of voltage pulses. The design and operation of FRAM devices are well known to those having skill in the art and need not be described further herein.
In fabricating integrated circuit ferroelectric capacitors, it is desirable that the fabrication steps for the integrated circuit that are performed after fabricating the ferroelectric capacitors not degrade the ferroelectric characteristics of the ferroelectric material. As is well known to those having skill in the art, a conventional ferroelectric memory generally is fabricated by first fabricating a field effect transistor in an integrated circuit substrate. The field effect transistor includes an insulated gate electrode between spaced apart source/drain regions in the integrated circuit substrate. An interlayer dielectric layer is then formed on the integrated circuit substrate including on the field effect transistor. A lower electrode, a ferroelectric layer and an upper electrode are then formed on the interlayer dielectric layer. Contact holes are opened in the interlayer dielectric layer to expose a source/drain region, the lower electrode and the upper electrode. A conductive layer is then deposited in the contact holes and on the interlayer dielectric layer to form a conductive interconnection.
In order to exhibit the ferroelectric hysteresis loop of
FIG. 1
, the ferroelectric material generally must retain its perovskite structure. Unfortunately, during the integrated circuit fabrication process steps after fabricating the ferroelectric capacitor, compression stresses and/or hydrogen may be produced which can affect the ferroelectric material structure, thereby reducing the remnant polarization. These deleterious effects may be produced when forming a dielectric layer on the ferroelectric capacitor.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit ferroelectric capacitors and methods of fabricating the same.
It is another object of the present invention to provide ferroelectric capacitors and fabrication methods that can reduce deleterious effects on the ferroelectric material during subsequent fabrication steps.
These and other objects are provided, according to the present invention, by fabricating an integrated circuit ferroelectric capacitor by forming on an integrated circuit substrate, a lower electrode adjacent the substrate, an upper electrode remote from the substrate and a ferroelectric layer therebetween, and forming a first low temperature oxide layer on the upper electrode, opposite the ferroelectric layer. The low temperature oxide may be annealed in oxygen. A second low temperature oxide layer may be formed on the first low temperature oxide layer, opposite the upper electrode, and the second low temperature oxide layer may be annealed in oxygen. The first and second low temperature oxide layers preferably comprise at least one of Plasma Enhanced Tetraethoxysilane (PE-TEOS), Undoped Silicon Glass (USG) and Electron Cyclotron Resonance Oxide (ECR-OX). An electrical contact to the lower electrode may be formed between the steps of forming a first low temperature oxide layer and a second low temperature oxide layer.
The low temperature oxide layers act as dielectric layers that apply tensile stress to the ferroelectric layer. This contrasts from conventional dielectric layers that generally are formed on integrated circuit capacitors. These conventional dielectric layers may apply compressive stress to the ferroelectric layer and thereby reduce the remnant polarization thereof.
Integrated circuit capacitors according to the present invention comprise a lower electrode on an integrated circuit substrate, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer such that the lower electrode is adjacent the substrate, the upper electrode is remote from the substrate and the ferroelectric layer is therebetween. A first layer comprising low temperature oxide is provided on the upper electrode, opposite the ferroelectric layer. A second layer comprising low
Chaudhari Chandra
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
LandOfFree
Methods of fabricating integrated circuit ferroelectric... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of fabricating integrated circuit ferroelectric..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabricating integrated circuit ferroelectric... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2888227