Methods of fabricating field effect transistors by first...

Details Methods of fabricating field effect transistors by first... Methods of fabricating field effect transistors by first...

1999-05-04

2001-06-12

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S530000

Reexamination Certificate

active

06245624

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit fabrication methods, and more particularly to methods of fabricating integrated circuit Field Effect Transistors (FET), often referred to as Metal Oxide Semiconductor (MOS) FETs.
BACKGROUND OF THE INVENTION
Integrated circuit field effect transistors are widely used in microelectronic devices. As the integration density of integrated circuits continues to increase, the size of the field effect transistors in the integrated circuit may continue to decrease. Unfortunately, as the size continues to decrease below half micron channel length, short channel effects arise that may degrade the performance of the field effect transistor. Short channel effects may occur when the depletion regions of the source/drain regions of the field effect transistor expand into the channel to reduce the length of the effective channel. This may cause the threshold voltage to drop and/or other undesired effects.
In order to reduce short channel effects it is known to reduce the thickness of the gate insulating layer, the width of the depletion region under the gate and/or the doping concentration of the integrated circuit substrate. It is also known to provide shallow source/drain junction regions.
It is also known to provide integrated circuit field effect transistors with both lightly doped and heavily doped source/drain regions. It will be understood that the terms “lightly doped” and “heavily doped” refer to doping levels relative to one another. Thus, for example, lightly doped source/drain structures also include moderately doped source/drain structures that can provide a higher doping level than a conventional lightly doped source/drain structure while still being lightly doped relative to the heavily doped source/drain structure. Unfortunately, the increased doping level in a moderately doped source/drain structure may worsen short channel effects.
A conventional fabrication method for integrated circuit field effect transistors including both lightly doped source/drain regions and heavily doped source/drain regions is described in U.S. Pat. No. 5,710,450 to Chau et al., entitled “
Transistor with Ultra Shallow Tip and Method of Fabrication.”
In such a conventional integrated circuit field effect transistor fabrication method, a gate insulating film is formed on an integrated circuit substrate such as a silicon semiconductor substrate. A gate electrode, preferably comprising polysilicon, is formed on the gate insulating layer. Then, lightly doped source/drain regions having shallow junctions are formed using the gate electrode as an ion implantation mask. Gate spacers are formed on the sidewalls of the gate electrodes. Heavily doped source/drain regions are formed, that are heavily doped relative to the lightly doped source/drain regions, using the gate electrode and the gate spacers as an ion implantation mask. The resultant structure is thermally treated thereby forming an integrated circuit field effect transistor. See also U.S. Pat. No. 5,215,937 to Erb et al., entitled “
Optimizing Doping Control in Short Channel MOS.”
In a conventional method, after the shallow junction of the lightly doped source/drain (including a moderately doped source/drain) is formed, gate spacer formation may be performed at temperatures of between about 450° C. to about 600° C. Moreover, after the ion implantation of the heavily doped source/drain region, a thermal anneal may be performed at about 1000° C. Unfortunately, the gate spacer formation process and/or the thermal treatment may cause redistribution of silicon atoms and diffusion of dopants within the integrated circuit substrate. Short channel effects may therefore increase and the performance of the integrated circuit field effect transistor may degrade.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of fabricating integrated circuit field effect transistors.
It is another object of the invention to provide methods of fabricating integrated circuit field effect transistors that can reduce short channel effects.
It is still another object of the present invention to provide methods of fabricating integrated circuit field effect transistors that can reduce redistribution of silicon atoms and/or diffusion of dopants within an integrated circuit substrate under high temperature process conditions, while still allowing shallow junctions to be formed.
These and other objects are provided, according to the present invention, by forming heavily doped source/drain regions in an integrated circuit substrate prior to forming lightly doped source/drain regions in the integrated circuit substrate. High temperature thermal processing preferably is carried out prior to forming the lightly doped source/drain regions in the integrated circuit substrate. Reduced short channel effects may thereby be obtained while still achieving shallow junctions.
More specifically, methods of fabricating integrated circuit field effect transistors according to the present invention form an insulated gate electrode comprising polysilicon on an integrated circuit substrate. The insulated gate electrode is oxidized. A gate spacer is formed on the oxidized sidewalls of the insulated gate electrode. Heavily doped source/drain regions are formed in the integrated circuit substrate by first implanting ions into the integrated circuit substrate using the insulated gate electrode and the gate spacer on the oxidized sidewalls of the insulated gate electrode as an implantation mask. The gate spacer is removed from the oxidized sidewalls of the insulated gate electrode after performing the step of forming heavily doped source/drain regions in the integrated circuit substrate. Finally, lightly doped source/drain regions, that are lightly doped relative to the heavily doped source/drain regions, are formed in the integrated circuit substrate. The lightly doped source/drain regions are formed by implanting ions into the integrated circuit substrate using the insulated gate electrode as an implantation mask, after performing the step of removing the gate spacer from the oxidized sidewalls of the insulated gate electrode.
In a particular embodiment, a buffer layer is formed on the integrated circuit substrate including on the oxidized insulated gate electrode, between the steps of oxidizing the insulated gate electrode and forming a gate spacer on the oxidized sidewalls of the insulated gate electrode. The gate spacer is then formed on the buffer layer on the oxidized sidewalls of the insulated gate electrode.
Preferably, the insulated gate electrode is oxidized to form an oxide film of thickness between about 20 Å and about 100 Å A thereon. Moreover, the gate spacer preferably comprises material that has an etch selectivity relative to the buffer layer. For example, the gate spacer may comprise oxide and the buffer layer may comprise silicon oxynitride (SiON). The silicon oxynitride may have a thickness of between about 100 Å and about 300 Å.
The heavily doped source/drain regions may be annealed prior to forming the lightly doped source/drain regions. Moreover, silicide may be formed on the gate electrode and on the heavily doped source/drain regions prior to forming the lightly doped source/drain regions.
After forming the lightly doped source/drain regions, rapid thermal annealing may be performed on the integrated circuit substrate including the lightly doped source/drain regions. The rapid thermal annealing process may be performed at a temperature between about 900° C. and about 1000° C. for between about 10 seconds to about 30 seconds after a ramp-up time of between about 5 seconds and about 20 seconds. The temperature may be increased in two steps to reduce the ramp-up time.
Accordingly, an integrated circuit field effect transistor may be fabricated by forming an insulated gate electrode including a gate spacer on the sidewall thereof on an integrated circuit substrate. Heavily doped source/drain regions are formed in the integrated circuit su

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