Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-26
2003-08-19
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S387000, C438S397000
Reexamination Certificate
active
06607954
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-88063, filed Dec. 29, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to fabrication methods for semiconductor devices, and more particularly to fabrication methods for cylinder-type capacitors in a semiconductor device.
BACKGROUND OF THE INVENTION
Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon, and thereby store data. As the integration density of integrated circuit devices, such as DRAM devices, continues to increase, it may be desirable to maintain sufficiently high storage capacitance while decreasing the area of the integrated circuit substrate that is occupied by each capacitor.
In order to increase the amount of capacitor per unit area of the integrated circuit substrate, it is known to use three-dimensional capacitor structures that can increase the effective area thereof. One type of three-dimensional capacitor structure is a cylindrical capacitor, also referred to herein as a cylinder-type capacitor. Cylinder-type capacitors are well known to those having skill in the art and are described, for example, in U.S. Pat. No. 6,258,691, entitled Cylindrical Capacitor and Method for Fabricating Same, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
As is well known to those having skill in the art, an integrated circuit capacitor generally includes a first or lower electrode, also referred to as a storage node, a dielectric layer on the first or lower electrode, and a second or upper electrode on the dielectric layer opposite the first or lower electrode. In a cylinder-type capacitor, at least part of the lower electrode is cylindrical in shape.
As the integration density of integrated circuit memory devices continues to increase, it may be desirable to increase the height of the cylinder-type capacitor, for example, by increasing the height of the lower electrode in the cylinder-type capacitor. Conventionally, the lower electrode of the cylinder-type capacitor is formed by etching a polysilicon layer using a hard mask layer pattern, rather than a photoresist pattern, as an etch mask. An array of cylinder-type capacitors may be formed in a cell array area of a semiconductor substrate and peripheral circuitry for the memory device may be formed in a peripheral circuit area of the semiconductor substrate.
However, when the polysilicon layer, which forms the lower electrode of the cylinder-type capacitor, is etched by using the hard mask layer pattern as an etch mask, the hard mask layer pattern of a cell array area of the substrate may become thin due to the three-dimensional etching of the array of lower electrodes, while the hard mask layer pattern in a peripheral circuit area of the substrate may remain thick from only one-dimensional etching. Stated differently, the pattern density of the cell array area in the semiconductor device generally is high while the pattern density of the peripheral circuit area generally is low. In any event, a step may be formed between the cell array area and the peripheral circuit area.
When the step is generated between the cell array area and the peripheral circuit area, and the hard mask layer pattern is removed to separate the lower electrodes of the cylinder-type capacitor for the memory cells in subsequent process steps, the height of the cylinder-type capacitor lower electrode in the cell array area may be reduced, and/or the hard mask layer pattern may remain in the peripheral circuit area. Moreover, when separating the lower electrodes of the cylinder-type capacitor for the memory cells, Chemical Mechanical Polishing (CMP) may be used to remove the hard mask layer pattern. However, the cost of the CMP may be high.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide fabrication methods for a capacitor in a semiconductor device, such as a semiconductor memory device, by forming a mold layer on a semiconductor substrate that includes a peripheral circuit area and a cell array area which includes a plug in a buried contact hole. A hard mask layer pattern is formed on the mold layer. The mold layer is etched, using the hard mask layer pattern as an etch mask, to form a mold layer pattern. In some embodiments, the hard mask layer pattern is then only partially etched back on the mold layer pattern. In other embodiments, the hard mask layer is completely removed from the mold layer pattern. A capacitor lower electrode is formed along the walls of the buried contact hole and on a surface of the mold layer pattern. A capacitor dielectric layer is formed on the capacitor lower electrode and a capacitor upper electrode is formed on the capacitor dielectric layer.
Other embodiments of the present invention successively form an etch stop layer and a mold layer on a semiconductor substrate including a peripheral circuit area and a cell array area in which a plug in a buried contact hole is formed. A hard mask layer pattern then is formed on the mold layer. The hard mask layer pattern comprises a polysilicon layer in some embodiments.
The mold layer and the etch stop layer are etched by using the hard mask layer pattern as an etch mask so that a mold layer pattern and an etch stop layer pattern are formed to expose a surface of the plug. In some embodiments, the etch stop layer comprises a silicon nitride layer, and the mold layer comprises a silicon oxide layer. After forming the mold layer pattern and the etch stop layer pattern, the plug may be further etched.
Then, the hard mask layer pattern is etched back so as to reduce a step between the hard mask layer pattern of the cell array area and the hard mask layer pattern of the peripheral circuit area. When etching back the hard mask layer pattern, the plug may be completely removed in some embodiments, or a portion of the plug may remain in other embodiments. In still other embodiments, a portion of the hard mask layer pattern may remain on the mold layer pattern when etching back the hard mask layer pattern.
A conductive layer for the capacitor lower electrode is formed along the walls of the buried contact hole and on a surface of the mold layer pattern. A sacrificial layer is formed between the buried contact hole and the mold layer pattern. In some embodiments, the sacrificial layer comprises a photoresist layer and/or a silicon oxide layer. In some embodiments, the sacrificial layer is etched back after the formation of the sacrificial layer. The etch back of the sacrificial layer may be performed so that the surface of the sacrificial layer is aligned with or lower than the surface of the mold layer pattern.
A capacitor lower electrode of the cylinder-type is formed by etching back the conductive layer for the capacitor lower electrode. In some embodiments, the hard mask layer pattern remaining on the mold layer pattern is removed when the conductive layer for the capacitor lower electrode is etched back. A cylinder-type capacitor may be completed by removing the mold layer pattern and the sacrificial layer, and forming a capacitor dielectric and upper electrode.
Fabrication methods for a cylinder-type capacitor according to some embodiments of the present invention etch back the hard mask layer pattern during formation of the cylinder-type lower electrode by using the hard mask layer pattern as an etch mask. Accordingly, a step between the hard mask layer pattern of the cell array area and the hard mask layer pattern of the peripheral circuit area can be reduced. As a result, the height of the cylinder-type capacitor lower electrode may not be lowered when separating the cylinder-type capacitor lower electrodes for the memory cells, and the cylinder-type capacitor lower electrodes
Chi Kyeong-koo
Hahm Jin-hwan
Jeon Jeong-sic
Kang Chang-jin
Fourson George
Garcia Joannie Adelle
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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