Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-20
2001-03-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S629000, C438S639000
Reexamination Certificate
active
06200849
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and fabrication methods therefor, and more particularly to contacts for integrated circuit memory devices and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices, such as Dynamic Random Access Memory (DRAM) devices are widely used in consumer and commercial products. As is well known to those having skill in the art, integrated circuit memory devices generally include a cell area containing a large array of integrated circuit memory cells and a core area containing peripheral circuits that are used to control the integrated circuit memory cells.
As the integration density of integrated circuit memory devices continues to increase it may become increasingly difficult to provide conductive contacts to the cell area and to the core area of integrated circuit memory devices. More particularly, as is well known to those having skill in the art, integrated circuit memory devices include conductive wiring layers and interconnections that are separated by dielectric layers that overlie an integrated circuit memory substrate. It is generally desirable to provide selective electric contacts from upper level wiring layers to active regions in the integrated circuit substrate, including but not limited to source and drain regions of field effect transistors that comprise the memory cell array and the core circuits.
As the integration density of integrated circuits continues to increase the topology of integrated circuit memory devices may become more nonuniform and the aspect ratio of the contact holes may become larger.
As to topology, the multiple levels of insulating layers and conductive wiring layers in high density memory devices may make the surface of the memory device nonplanar, and thereby create large topography differences in the device. Thus, it is known that the height of the cell area may differ from that of the core area by more than 2 &mgr;m, for example due to the presence of a stacked cell capacitor over the bit lines in the cell area.
Moreover, as the number of insulating layers and wiring layers continues to increase and the size of the active devices Such as transistors continues to decrease, the aspect ratio of the contact holes may continue to increase. For example, a technical report entitled
The National Technology Roadmap for Semiconductors
, published in 1997 by the Semiconductor Industry Association (SIA), discloses that the aspect ratio of a 0.1 &mgr;m process may be as much 9:1, while the aspect ratio of a 0.35 &mgr;m process may only be approximately 4.5:1. Since the ground rules for 256 MB DRAMs have now been reduced down to about 0.2 &mgr;m, the aspect ratio of the contact holes may be quite large.
Many attempts have been made to overcome the problems of nonuniform topologies and high aspect ratios. For example, photoresist reflow processes may be used to planarize an integrated circuit substrate and reduce the topological differences thereon. See. for example, U.S. Pat. No. 5,616,625 to McNamara et al., U.S. Pat. No. 5,268,333 to Lee et al.; and U.S. Pat. No. 5,851,874 to Kuo et al. Another attempt to planarize the surface of integrated circuit devices is described in U.S. Pat. No. 5,532,191 to Nakano et al., wherein Chemical Mechanical Polishing (CMP) is used for planarization. Unfortunately, photoresist reflow processes and CMP may not be able to fully planarize the topography of integrated circuit memory devices, or may introduce problems of their own.
Attempts also have been made to form high aspect ratio contacts for integrated circuit memory devices. See, for example, U.S. Pat. No. 5,677,557 to Wuu et al. Unfortunately, these processes may be complicated and it may be difficult to integrate the formation of conductive contacts in the cell area and in the core area of integrated circuit memory devices. Specifically, separate two-step processes may be employed for making conductive contacts in the cell area and in the core area. Direct contacts to the cell area and the core area of an integrated circuit memory device may be formed separately by exposing and processing the contacts for the cell area and the core area separately. Accordingly, there continues to be a need for methods and structures that can provide conductive contacts to a cell area and to a core area of an integrated circuit memory device, that can provide reduced topology and/or that can accommodate high aspect ratios.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of fabricating conductive contacts for integrated circuit memory devices and integrated circuit memory devices so fabricated.
It is another object of the present invention to provide methods of fabricating conductive contacts to a cell area and to a core area of integrated circuit memory devices wherein the contacts may be formed simultaneously, notwithstanding a large topology difference between the cell area and the core area.
It is another object of the present invention to provide contact fabrication methods and contacts so fabricated that can reduce the photolithographic requirements for forming a contact in a cell area, to thereby allow formation of high aspect ratio conductive contacts.
These and other objects are provided, according to the present invention, by methods of fabricating conductive contacts to a cell area and to a core area of integrated circuit memory devices, by forming a first interlayer dielectric layer on the cell area and on the core area, including on a plurality of spaced apart insulated gates in the cell area. The first interlayer dielectric layer includes therein a plurality of first contact holes having sidewalls that extend from a face of the first interlayer dielectric layer through the first interlayer dielectric layer. The first contact holes further extend between the plurality of spaced apart insulated gates. A first recessed conductive layer is formed in the plurality of first contact holes, between the plurality of spaced apart insulating gates, and recessed beneath the face of the first interlayer dielectric layer. A second dielectric layer then is conformally formed on the face of the first dielectric layer, on the sidewalls of the first contact holes and on the first recessed conductive layer in the first contact holes. At least a portion of the second dielectric layer is removed from on the first recessed conductive layer. A second conductive layer is formed in the first contact holes between the second dielectric layer on the sidewalls of the first contact holes. Thus, high aspect ratio contacts to the cell area may be provided.
Second contact holes then may be formed in the core area, extending through the second dielectric layer and the first dielectric layer. A third conductive layer then may be conformally formed on the second dielectric layer, on the second conductive layer and lining the second contact holes. Thus, conductive contacts for the core area and the cell area may be formed simultaneously.
A fourth conductive layer then may be formed on the third conductive layer in the second contact holes. A bit line then may be formed on the second conductive layer in a selected one of the first contact holes. The bit line extends onto the second dielectric layer adjacent the selected one of the first contact holes. The bit line is spaced apart from the second conductive layer in the first contact holes that are adjacent the selected one of the first contact holes. Thus, the likelihood of shorting between the bit line and a buried contact in the cell area may be reduced and preferably eliminated.
The third conductive layer preferably is formed by forming a conformal refractory metal layer on the second dielectric layer, on the second conductive layer and lining the second contact holes. A titanium nitride layer then may be formed on the refractory metal layer. Annealing is performed to form a silicide from the conformal refractory metal layer and the titanium nitride layer. The bit line preferably i
Fourson George
Garcia Joannie A.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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