Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1999-01-12
2003-01-28
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S771000, C438S787000, C438S788000
Reexamination Certificate
active
06511921
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a system and process for surface passivation of a semiconductor substrate surface. More particularly the present invention relates to a system and process for surface passivation, which produces a passivated semiconductor substrate surface that allows for effective characterization of the electrical properties of the semiconductor substrate layer underlying the passivated substrate surface.
Regardless of the cleanliness of the semiconductor wafer processing environment, some electrically active contaminants end up in or on the semiconductor wafer surface. In order to protect the wafer or its surface from such contaminants, the top layer of the wafer surface, which typically includes silicon, is oxidized to serve as a protective coating. During the wafer surface oxidation or passivation process, as it is commonly known, the top layer of silicon is converted to silicon oxide or some other semiconductor oxide.
FIG. 1
shows a portion of a semiconductor wafer
10
having a bulk silicon layer
14
, above which is disposed a silicon dioxide (SiO
2
) layer
12
(hereinafter interchangeably referred to as the “oxide layer” or “passivated surface”) that may be fabricated by surface passivation techniques described below. In the presence of such a passivated surface, contaminants landing on the wafer surface end up on the new oxide layer
12
away from the electrically active semiconductor layer or the bulk silicon layer
14
. However, contaminants disposed above the oxide layer impede the electrical characterization of bulk silicon layer
14
underlying the passivated wafer surface (hereinafter referred to as the “underlying layer
14
” to facilitate discussion). The electrical characterization, e.g., resistivity being most common, of underlying layer
14
is an important specification desired by a purchaser or consumer of semiconductor wafers and/or chips because, among other factors, the electrical properties of underlying layer
14
significantly impact the electrical performance of the active devices formed in the underlying layer.
The wafer surface passivation process, i.e. fabrication of oxide layer
12
of
FIG. 1
, is currently accomplished either through wet chemistry or by thermal oxidation. According to the wet chemistry method, the wafer surface, which is typically includes silicon, is exposed at low temperatures, e.g., about 80° C., to an aqueous oxidizing solution that oxidizes or passivates the wafer surface and forms silicon dioxide (SiO
2
) thereon. There are oxidizing solutions of different compositions that are commercially available to accomplish wafer surface oxidation. Some compositions of the commercially available oxidizing solution are proprietary. Other compositions of the oxidizing solution, however, are well known. A representative aqueous oxidizing solution composition includes hydrogen peroxide, hydrogen fluoride, ammonium fluoride, etc. Another representative aqueous oxidizing solution composition includes ozone and hydrogen fluoride. After the wafer surface is oxidized using wet chemistry, it undergoes drying which requires a drying apparatus and additional equipment associated with such an apparatus.
Although the wet chemistry method passivates the wafer surface at the desired relatively low temperatures, it suffers from several drawbacks. By way of example, the wet chemistry surface method produces an oxide layer of poor quality that does not allow for simple and reproducible measurements of the electrical properties of the underlying layer. Consequently, it is difficult to ensure a purchaser or consumer of semiconductor wafer and/or chips that the electrical properties of the underlying layer meets their specifications, without utilizing destructive measurement techniques.
As another example, after the wafers are exposed to a wet chemistry solution, they are dried using a drying apparatus, which requires added cost and space for additional equipment. The wet chemical passivation and drying steps are also time consuming and, therefore, lower the throughput of the wafer surface passivation process. The problems associated with limited cost and space are further aggravated when additional resources are expended for environmentally safe disposal of the wet chemistry solutions.
As yet another example, the wet chemistry approach described above may also introduce contaminants from the oxidizing solution on the wafer surface. These contaminants include dissolved metals or particles and may also exacerbate the problem of measuring the electrical properties of the underlying layer.
Thermal oxidation is another method that is traditionally employed to accomplish surface passivation. Those skilled in the art recognize that thermal oxidation offers many advantages associated with dry processing, i.e. processing in the absence of an aqueous oxidizing solution, that are not realized by the wet chemistry method. A few advantages of dry processing by thermal oxidation include eliminating contamination caused by the aqueous oxidizing solution and the need for a drying apparatus and other equipment used in conjunction with the drying apparatus.
Thermal oxidation typically begins when a wafer is loaded into a tube furnace containing an oxidizing environment and the temperature inside the furnace is raised to relatively high temperatures, e.g., 900° C. and higher. An oxidizing environment may contain oxygen or ozone in various concentrations. Any ozone gas used in the tube furnace is produced ex-situ, i.e. outside the tube furnace, and is transported inside the tube furnace through appropriate equipment, such as pipes, valves and the like, during thermal oxidation. In order to accomplish the required extent of passivation, the wafer is exposed to such high temperatures for about 2 hours or more. The heated wafer surface is cooled before the electrical properties of the underlying layer are determined.
Another thermal oxidation technique involves oxidizing the wafer at temperatures of about 1000° C. and higher in a Rapid Thermal Oxidation (RTO) apparatus for a short period of time, e.g., 30 seconds. In order to make the electrical properties of the underlying layer measurable, the oxidized wafer surface is subjected to Rapid Thermal Annealing (RTA) in a nitrogen and/or argon gas environment maintained at the same relatively high temperatures as the oxidation process.
Unfortunately, the thermal oxidation techniques discussed above also suffer from several drawbacks. By way of example, the dopant concentration profile, the oxygen precipitation level and mechanical properties of the wafer are not preserved due to the high thermal budget of the thermal oxidation process.
FIG. 2
shows a portion of a epitaxial silicon wafer
20
having a passivated surface and the layer stack of this wafer is discussed hereinafter as an example to facilitate discussion regarding the undesirable effects of high temperature treatments on a wafer during thermal oxidation.
Epitaxial silicon wafer
20
includes an epitaxial silicon layer
24
fabricated above a bulk silicon layer
26
. Those skilled in the art will recognize that epitaxial silicon layer has a greater degree of silicon purity than bulk silicon layer
26
, which may be more conductive due to a higher dopant concentration than epitaxial layer
24
. Furthermore, the high purity of the epitaxial layer makes it suitable for many applications and is generally a desired feature by purchasers or consumers of semiconductor wafers and/or chips. An oxide layer
22
, as shown in
FIG. 2
, is fabricated above epitaxial layer
24
to reduce the reactivity of the surface of epitaxial silicon wafer
20
.
FIG. 3
shows a graph of resistivity, which is shown on vertical axis
32
, versus the depth of the epitaxial silicon wafer from the top of the epitaxial layer, which depth is shown on horizontal axis
34
. It is well known to those skilled in the art that the resistivity of a layer is inversely proportional to the dopant concentration in that layer and, therefore, the resistivity of ep
Huber Walter
Madsen Jonathan M.
Panczyk Christopher A.
Duong Khanh B.
Jr. Carl Whitehead
Squire Sanders & Dempsey L.L.P.
Sumco Phoenix Corporation
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