Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-02
2001-12-11
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S397000, C257S306000
Reexamination Certificate
active
06329241
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for producing capacitor-node contact plugs, and more particularly to a method for producing capacitor-node contact plugs in a DRAM (Dynamic Random Access Memory).
2. Description of the Prior Art
Prior semiconductor memory devices, for example the Dynamic Random Access Memory(DRAM), generally exist in the form of matrix, as shown in FIG.
1
. In a semiconductor substrate with a T shape active region (AC), several parallel word lines (WL) arc formed. Next, on the sides of the word lines in the T shape region, source regions (S) and drain regions (D) are formed. Bit line contact pads (BC) are formed and coupled to an extend region (ED) of the T shape active region. A capacitor-node contact plug (CC) is coupled to the source region in turns. The extend region is the extension of the drain region. Bit lines are formed and coupled to the bit lines contact pads (BC), which are vertical to the word lines.
However, due to the trend for reducing the size of the DRAM, the contact area of the capacitor-node contact plugs with the landing pads or source regions in the lower layer is reduced. Because the capacitor-node contact plugs can touch the bit lines and the word lines easily, the formation of the capacitor-node contact plugs is more difficult, and the tolerance may not increase effectively.
SUMMARY OF THE INVENTION
To overcome the above-mentioned problems, the present invention provides a method for producing capacitor-node contact plugs of a dynamic random access memory, comprising: providing a semiconductor substrate; forming at least one gate structure separated by a first isolation layer as a word line, and forming a source region and a drain region next to the word line; forming a second isolation layer to cover the first isolation layer, word line, source region, and drain region; forming a first landing pad, which passes through the second isolation layer and couples to the source region, wherein the first landing pad is offset a given distance along the word line; forming a third isolation layer to cover the second isolation layer and the first landing pad; forming a second landing pad coupled to the drain region through the second isolation layer and the third isolation layer; forming at least one bit line separated by a fourth isolation layer along the vertical direction to the word line, wherein the at least one bit line is coupled to the second landing pad; forming a fifth isolation layer to cover the at least one bit line separated by the fourth isolation layer; and forming a capacitor-node contact plug, which is coupled to the side wall and a part of the top of the first landing pad through the fifth isolation layer, the third isolation layer, and the second isolation layer.
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Diaz José R
Kilpatrick & Stockton LLP
Lee Eddie
Marcou George T.
Nanya Technology Corporation
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