Methods for manufacturing semiconductor memory devices

Details Methods for manufacturing semiconductor memory devices Methods for manufacturing semiconductor memory devices

2003-04-28

2004-06-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06743678

ABSTRACT:

RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2002-0067744, filed Nov. 4, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a metal-insulating layer-metal (MIM) capacitor.
BACKGROUND OF THE INVENTION
As the integration density of semiconductor devices has increased, the available area for devices has decreased. With less available area, capacitors that are used for storing information in a DRAM may need to provide an equivalent or greater capacitance in less area. Some approaches for reducing capacitor area include, forming a lower electrode of a capacitor in a three-dimensional shape, such as a cylinder or a fin, increasing a surface area of the lower electrode by covering it with a hemispherical grain, reducing the thickness of a capacitor dielectric layer, and using a high k-dielectric material or a ferroelectric material as a dielectric layer.
When high k-dielectric materials, such as Ta
2
O
5
or BST((Ba,Sr)TiO
3
), are used for a dielectric layer, polysilicon may not be useful as a capacitor electrode because of tunneling that may occur through the dielectric layer and a resulting leakage current. For this reason, noble metals having a very high work function, such as platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), and osmium (Os), are often used for capacitor electrodes when a dielectric layer is formed from high k-dielectric materials or ferroelectric materials. Ruthenium, which may be etched by a plasma containing oxygen, is widely used for electrodes of metal-insulating layer-metal (MIM) capacitors.
FIG. 1
is a cross-sectional view of an MIM capacitor using ruthenium for a lower electrode. An interlayer dielectric layer (ILD)
15
is formed on a semiconductor substrate
10
. A contact plug
20
is formed in the ILD
15
. The contact plug
20
may be a material, such as titanium nitride (TiN), which does not react with a later formed ruthenium lower electrode. A mold oxide layer (not shown) is deposited to a predetermined thickness on the ILD
15
. A predetermined portion of the mold oxide layer is etched to expose the contact plug
20
and to form a region on which a lower electrode can be formed (not shown).
A lower electrode material is deposited on the mold oxide layer. The mold oxide layer is exposed using chemical mechanical polishing (CMP) or an etchback process to form a concave-type lower electrode
25
. The mold oxide layer is then removed.
A tantalum oxide (Ta
2
O
5
) layer
30
is formed on the lower electrode
25
and the ILD
15
to serve as a dielectric layer. A thermal process is applied to the tantalum oxide layer
30
at a temperature of 600 to 700° C. to improve its dielectric characteristics. An upper electrode
35
, such as ruthenium, is formed on the tantalum oxide layer
30
to provide the capacitor
40
.
When the high-temperature thermal process is applied to the tantalum oxide layer
30
, an agglomeration may occur from a growth of crystal grains on a surface of the ruthenium lower electrode
25
. Such crystal grain growth and the agglomeration on the surface of the upper electrode
35
may occur even if the high-temperature thermal process occurs after the upper electrode
35
is formed.
FIG. 2A
illustrates an SEM photograph after a ruthenium lower electrode is deposited, and
FIG. 2B
illustrates an SEM photograph after a high-temperature thermal process is applied to the tantalum oxide layer
30
. Referring to
FIG. 2A
, the ruthenium metal layer (the lower electrode) has a uniform surface immediately after the deposition. However, after a predetermined temperature is applied during the thermal process, the surface of the lower electrode
25
experiences crystal grain grown and agglomeration as shown in FIG.
2
B. As shown in
FIG. 2B
, the surface of the lower electrode
25
becomes non-uniform due to the agglomeration. Additionally, the agglomeration may cause the thickness of the dielectric layer, i.e., the tantalum oxide layer
30
to be changed. Moreover, the agglomeration may cause adhesion of the lower electrode
25
to the tantalum oxide layer
30
to be degraded and may result in generation of a leakage current.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide methods for manufacturing semiconductor memory devices. According to some embodiments, a lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.
According to other embodiments of the present invention, a first metal layer of a first metal is deposited on a semiconductor substrate. A second metal layer of a second metal, that is different than the first metal, is deposited on the first metal layer. A third metal layer of the first metal is deposited on the second metal layer opposite to the first metal layer. The third metal layer, the second metal layer, and the first metal layer are thermally treated to diffuse atoms from the second metal layer into the first and third metal layers and to form a lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.
According to other embodiments of the present invention, a first metal and a second metal are simultaneously deposited on a semiconductor substrate to form a lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.
According to other embodiments of the present invention, a lower electrode of a first metal is formed on a semiconductor substrate. Ions of a second metal are implanted into the lower electrode. The lower electrode is thermally treated to diffuse the implanted ions of the second metal into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.
According to yet other embodiments of the present invention, a lower electrode is formed on a semiconductor substrate. A dielectric layer is formed on the lower electrode. An upper electrode of a first metal is formed on the dielectric layer. Atoms of a second metal that is different than the first metal are diffused into the upper electrode.
Forming the lower electrode and/or the upper electrode from a first metal with diffused second metal may reduce or prevent crystal grain growth and agglomeration during a subsequent high temperature process. Accordingly, a dielectric layer formed on the electrode may have a more uniform thickness, and leakage current may be reduced.


REFERENCES:
patent: 5622888 (1997-04-01), Sekine et al.
patent: 5708302 (1998-01-01), Azuma et al.
patent: 5790366 (1998-08-01), Desu et al.
patent: 6218238 (2001-04-01), Huang et al.

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