Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-10-09
2001-12-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S683000, C438S750000, C438S755000
Reexamination Certificate
active
06331478
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 99-43209, filed Oct. 7, 1999.
FIELD OF THE INVENTION
The present invention relates to methods for manufacturing semiconductor devices, and more particularly, to methods for manufacturing semiconductor devices having self-aligned contact plugs.
BACKGROUND OF THE INVENTION
As the integration density of semiconductor devices continues to increase, the distance from contact holes that connect lower and upper interconnection layers to surrounding interconnections typically decreases and the aspect ratio of the contact holes typically increases. Thus, highly integrated semiconductor devices adopting a multilayered interconnection structure may require more accurate and strict processing conditions when contact holes are formed by using photolithography techniques. In manufacturing semiconductor devices having a design rule of 0.25 &mgr;m or less, current lithography techniques may not be sufficient to reproducibly perform desirable processes with the same accuracy.
In order to overcome limitations of photolithography in the formation of contact holes, self-alignment techniques have been suggested for forming contact holes. For example, self-alignment techniques employing nitride spacers as an etch stop layer in the formation of self-aligned contact holes have been suggested.
A conventional self-alignment technique is illustrated in FIG.
2
. In
FIG. 2A
, a lower structure, for example, a conductive layer
122
such as a gate electrode having a substantially rectangular section, is initially formed on a semiconductor substrate
120
via patterning provided by a general photolithography process. In
FIG. 2B
, a layer of nitride
124
is deposited on the entire surface of the conductive layer
122
. In
FIG. 2C
, the resultant structure is subjected to an etchback process so as to form nitride spacers
124
a
on the sidewalls of the conductive layer
122
. In
FIG. 2D
, an interlayer dielectric (ILD) film
126
is formed of an oxide layer on the structure. In
FIG. 2E
, a photoresist pattern
128
is formed on the ILD film
126
for exposing contact holes. In
FIGS. 2F and 2G
, the ILD film
126
is etched to form self-aligned contact hole
130
.
In the conventional self-aligned contact hole formation, the ILD film
126
is etched with a high degree of selectivity relative to the nitride spacers
124
a
, to form the contact hole
130
. During the etching process, carbon rich carbon fluoride gases, for example, C
4
F
8
or C
5
F
8
, may be used so as to increase the selectivity.
These gases may typically produce a large amount of polymers. Thus, if the etching conditions are set such that selectivity is increased, the amount of polymers produced by the etching increases. As a result, the etching may be stopped after formation of the ILD layer
126
a
but before formation of contact hole
130
, as illustrated, for example, in FIG.
2
F.
Alternatively, as illustrated in
FIG. 2G
, when the selectivity between the ILD film
126
and the nitride spacers
124
a
is decreased, ILD layers
126
a
and a complete contact hole
130
can be formed without the interruption due to the polymer. However, when the selectivity is low, the nitride spacers
124
a
may be etched together with the ILD film
126
during the etching process. Accordingly, the width Wn of the remaining nitride spacers
124
a
may be too small to provide a desired degree of insulation layer between the sidewalls of the conductive layers
122
and the contact hole
130
. Thus, a short between a self-aligned contact plug in the contact hole
130
and the conductive layers
122
may occur, for example, at exposed sidewall
122
s.
In the self-aligned contact hole formation for manufacturing large scale integration semiconductor devices, the process margin may be small even under optimal processing conditions, and thus it may be difficult to reproducibly produce devices with the same accuracy.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, methods for manufacturing semiconductor devices with an increased process margin may ensure that a desired insulation length between an electrically conductive line and a self-aligned contact plug is maintained during self-aligned contact hole formation when manufacturing highly integrated semiconductor devices.
According to aspects of the present invention, a method for manufacturing a semiconductor device includes forming a mask pattern on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove having silicon defects on the surface thereof. Then, the metal silicide layer with the shallow groove is isotropically etched in a second etchant to remove the silicon defects and to form a metal silicide layer with a smooth surface. Preferably, the first etchant is a mixture of NH
4
OH, H
2
O
2
and H
2
O, and the second etchant is a mixture of HNO
3
, CH
3
COOH, HF and H
2
O.
In other embodiments of the present invention, a method for manufacturing a semiconductor device includes forming a metal silicide layer on a semiconductor substrate. A mask pattern is formed on the metal silicide layer to expose a portion of the metal silicide layer, and the exposed portion of the metal silicide layer is isotropically etched in a first etchant using the mask pattern as an etching mask to form a metal silicide layer with a shallow groove. The metal silicide layer with the shallow groove is isotropically etched in a second etchant using the mask pattern as an etching mask to form a metal silicide layer with a recessed region having a smooth surface, which defines a undercut region beneath the bottom edge of the mask pattern. The exposed metal silicide layer is anisotropically etched using the mask pattern as an etching mask, to form a metal silicide pattern having lower edges substantially perpendicular to the major surface of the semiconductor substrate, and upper edges which are chamfered along the contour of the undercut region. Preferably, the second etchant etches silicon better than the first etchant. Preferably, the width of the top surface of the metal silicide pattern is defined by chamfers at both sides thereof, and is greater than half the width of the mask pattern.
In still other embodiments of the present invention, the semiconductor device manufacturing method further includes forming insulation spacers on the sidewalls of the mask pattern and metal silicide pattern. Interlayer dielectric patterns with a self-aligned contact hole therebetween, which exposes both the insulation spacers and an active region of the semiconductor substrate are formed. The self-aligned contact hole is filled with a conductive material to form a contact plug self-aligned with the metal silicide pattern.
In yet other embodiments of the present invention, the semiconductor device manufacturing method further includes forming an insulating layer on the metal silicide layer. A photoresist pattern is formed on the insulating layer. The insulation layer is etched using the photoresist pattern as an etching mask to form the mask pattern, and then the photoresist pattern is removed by an ashing process. Then, the residue is stripped off in a wet cleaning system. Here, the etching in the first etchant and the etching in the second etchant are continuously carried out in the wet cleaning system immediately after stripping off the residue.
According to the present invention, by forming smooth chamfers without defects on upper sidewall edges of the upper conductive layer of an electrically conductive line, such as a gate structure, insulation spacers having a sufficient width between the conductive layer and the contact plugs self-aligned therewith are provided, resulting in microelectronic devices having improved electrical properties. In addition, the undercut regions can be formed by efficiently utilizing etching processes which are currently used in the manufacture of semi
Hwang In-seak
Ko Yong-sun
Lee Keum-joo
Song Chang-Iyoung
Bowers Charles
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
Smoot Stephen W.
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