Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-03-01
2011-03-01
Arora, Ajay K (Department: 2892)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S149000, C438S631000, C257SE21190
Reexamination Certificate
active
07897500
ABSTRACT:
A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
REFERENCES:
patent: 6660573 (2003-12-01), Han
patent: 2004/0129981 (2004-07-01), Kim et al.
patent: 2006/0084247 (2006-04-01), Liu
patent: 2007-073887 (2007-03-01), None
patent: 1020040006421 (2004-01-01), None
patent: 1020040028384 (2004-04-01), None
Choi Gil-heyun
Jung Eun-Ji
Kim Byung-hee
Kim Dae-Yong
Kim Hyun-Su
Arora Ajay K
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
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