Methods for forming peripheral circuits including high voltage t

Details Methods for forming peripheral circuits including high voltage t Methods for forming peripheral circuits including high voltage t

1997-10-30

2000-06-06

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, H01L 21336, H01L 218238

Patent

active

060717750

ABSTRACT:
A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate insulating layer, a first gate electrode, first lightly doped regions in the well region adjacent opposite sides of the first gate electrode, and first heavily doped regions in the well region adjacent the first lightly doped regions opposite the first gate electrode. The first gate insulating layer is adjacent the first well region and has a first thickness. The first gate electrode is on the first gate insulating layer, and the first lightly doped regions define a first transistor channel therebetween and have a second conductivity type and a first light dopant concentration. The first heavily doped regions have the second conductivity and a first heavy dopant concentration. A second transistor on the well region includes a second gate insulating layer, a second gate electrode, second lightly doped regions in the second well region adjacent opposite sides of the second gate electrode, and second heavily doped regions in the second well region adjacent the second lightly doped regions opposite the second gate electrode. The second gate insulating layer has a second thickness less than the first thickness. The second lightly doped regions define a second transistor channel therebetween and have the second conductivity type and a second light dopant concentration. The second heavily doped regions have the first conductivity and a second heavy dopant concentration. Related methods are also discussed.

REFERENCES:
patent: 4471523 (1984-09-01), Hu
patent: 5182619 (1993-01-01), Pfiester
patent: 5329138 (1994-07-01), Mitani et al.
patent: 5355011 (1994-10-01), Takata
patent: 5472887 (1995-12-01), Hutter et al.
patent: 5573962 (1996-11-01), Sung
patent: 5573963 (1996-11-01), Sung
patent: 5773336 (1998-06-01), Gu
Wolf, "Silicon Processing for the VLSI Era vol. 2 Process Intergration" p 382 and pp 387-388, 1990.

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