Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2001-07-18
2003-03-18
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S240000, C438S287000, C438S785000
Reexamination Certificate
active
06534420
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to methods of forming dielectric materials and devices fabricated therewith. More specifically, the present invention relates to methods of forming high purity dielectric materials over a semiconductor substrate and devices formed therewith.
BACKGROUND
As the performance of integrated circuits (ICs) increases, both with regard to more complex functionality and higher speeds, there is a need for improved dielectric materials. Such performance increases are often obtained by scaling, that is decreasing the area or size of individual device components that are used to form such integrated circuits. One example of such scaling is the reduction of the gate length of a typical transistor which, over the past several years, has gone from several microns to fractions of a micron. Such scaling efforts have also resulted in a reduction in the physical size of capacitors used in a variety of ICs such as DRAMS and SRAMS (dynamic and static random access memories, respectively).
While such scaling efforts have generally resulted in the desired increases in performance and complex functionality, such reductions in area or size also impact at least some characteristics of the devices so “scaled.” For example, reducing the gate length of a transistor generally reduces the transistor's output and decreasing the size of a capacitor generally reduces the capacitance or amount of charge such a capacitor can store. Fortunately, changing other features of such devices has made it possible to at least control these changes. Thus as the gate length of the typical transistor has been reduced, the gate dielectric layer's thickness has also been reduced to at least partially compensate for what might otherwise be a change in device output. Similarly, as the size of capacitor structures has been reduced, materials such as hemispherically grained polysilicon (HSG) have been employed to increase the effective surface area of such structures and compensate, at least in part, for such size reductions. However, it appears likely that as scaling continues, such exemplary compensation techniques may not continue to provide acceptable results.
For example silicon dioxide (SiO
2
), with a dielectric constant of about 3.9, remains the most common material employed for gate dielectric layers. To maintain transistor output at an acceptable level, a transistor having a gate length of 0.1 micron will require a SiO
2
layer which is ultra-thin that is with a thickness of about 2 nanometers (nm). The forming and use of such ultra-thin SiO
2
layers is problematic for a variety of reasons since such layers consist of only a few layers of molecules. Thus only one additional or missing layer of molecules can have a dramatic effect on device performance; for example where a desired layer is four SiO
2
molecules thick, a change of one molecule will change a characteristic such as the layer's capacitance by as much as 25%. In addition, such thin layers typically exhibit high current leakage, for example due to band to band or Fowler-Nordheim tunneling. Such layers are also more susceptible to dopant penetration or diffusion through the layer thus changing the characteristics of an adjacent layer or region; for example boron diffusion from the gate electrode into the channel region can alter channel characteristics.
Alternative dielectric materials to SiO
2
that allow the forming of a thicker layer with acceptable dielectric properties are by virtue of their higher dielectric constant of interest. For the purpose of illustration, a gate dielectric layer formed of an alternative material having an appropriately high dielectric constant can allow for a thickness of that alternate material layer several times that of a SiO
2
layer while having the performance characteristics of the thinner SiO
2
layer. Thus the thicker alternative material gate dielectric layer is said to have the equivalent oxide thickness (EOT) of the thinner SiO
2
layer.
Alternate dielectric materials such as the oxides of titanium, aluminum, tantalum and others have therefore received attention as replacements for SiO
2
. However, such alternate materials generally need to exhibit, in addition to a dielectric constant greater than that of SiO
2
, a large band-gap with a favorable band alignment, low interface state density, good thermal stability and the ability to be formed in a manner consistent with known semiconductor process methods at reasonable cost and yield. Unfortunately, many candidate alternative materials having an appropriately high dielectric constant, and meeting these additional requirements are difficult to form. Also, even where such alternate materials can be formed, the methods currently known are generally problematic as resulting material layers often include contaminant moieties that reduce the integrity of the material from that which is desired. Thus it would desirable provide methods for forming such alternate dielectric materials and as well as the various semiconductor devices that can be formed therewith. It would be additionally desirable if such methods provided for the forming of the dielectric materials that are essentially free of contaminating moieties, thus having high-integrity. Finally it would be desirable for such methods to provide the desired dielectric material in a manner consistent with common semiconductor process methods and with high yield.
SUMMARY
Embodiments in accordance with the present invention provide methods of forming dielectric materials that are alternatives to materials such as SiO
2
, as well as semiconductor devices that employ such dielectric materials.
In an exemplary embodiment of the present invention, a semiconductor substrate is provided within a vacuum chamber. High purity metal is physically vapor formed over the semiconductor substrate to form a metal layer. After such forming, the metal layer is oxidized to form a dielectric material. The oxidation employs atomic oxygen generated in a high density plasma.
Some embodiments in accordance with the present invention provide for physically vapor forming the high purity metal layer by an evaporation process, for example an electron beam evaporation process that employs an electron beam evaporation apparatus. Such or other embodiments employ low energy ion-bombardment during the evaporation process. Where such ion-bombardment is provided, generally a low density beam of ions is directed towards the semiconductor substrate during the physical vapor forming of the metal layer.
Once a desired thickness of the high purity metal layer is formed, generally such metal layer is oxidized to form a dielectric or insulative material. Embodiments in accordance with the present invention generally provide for oxidizing the high purity metal layer by employing a source of atomic oxygen. Such or other embodiments generally form the atomic oxygen by providing a mixture of oxygen gas and a noble gas into a high density plasma formed by employing a microwave power source to provide microwave energy at an appropriate frequency and power level.
Some embodiments of the present invention encompass semiconductor devices such as transistors, capacitors and the like, that employ dielectric material layers formed in accordance with the present invention. Such and other embodiments in accordance with the present invention encompass integrated circuits such as dynamic and static random memories (DRAMs and SRAMs) that employ transistors, capacitors and the like formed in accordance with the present invention. Such integrated circuits are formed having dielectric material layers formed in accordance with the methods of the present invention. Some semiconductor device embodiments of the present invention encompass a dielectric material layer having an equivalent oxide thickness (EOT) of 2 nanometers or less.
REFERENCES:
patent: 5494840 (1996-02-01), Ohmi
patent: 5999379 (1999-12-01), Hsiao et al.
patent: 6261917 (2001-07-01), Quek et al.
patent: 6303427 (2001-10-01), Song et al.
patent: 6391727 (2
Ahn Kie Y.
Forbes Leonard
Brophy Jamie L.
Wells St. John P.S.
Zarabian Amir
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