Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-05-25
2003-06-03
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S618000, C438S710000
Reexamination Certificate
active
06573168
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-35950, filed Jun. 28, 2000, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to methods for manufacturing integrated circuit devices, and more particularly, to methods for forming conductive contact bodies in an interdielectric layer.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuit devices increases, misalignment margin in photolithographic processes may become narrower. As a result, it may not be easy to obtain a sufficient misalignment margin when manufacturing the integrated circuit devices. Thus, an electrical short-circuit can occur between a gate line and a contact pad adjacent to the gate line, between a bit line and a buried contact (BC) adjacent to the bit line, and/or between the gate line and the BC or a direct contact (DC).
In order to overcome this problem, Self-Aligned Contact (SAC) etching processes have been implemented. However, SAC etching processes may have limitations with respect to failure to open a contact hole and/or selectivity.
More specifically, in order to obtain a high selectivity, the etching process may be implemented as a polymer enrich process, which is an etching process that generates enriched polymer during etching. However, this etching process may generate a lag in etching similar to Reactive Ion Etching (RIE). Dry etching performed under these conditions may deteriorate the uniformity of the dry etching on a substrate, thus making it desirable to increase the amount of over etching. This can cause the selectivity to be reduced.
Also, the high-integration density of integrated circuit devices may make it desirable to increase the aspect ratio of a contact hole being filled with a contact body. In order to obtain an adequate insulating shoulder, an adequate thickness of silicon nitride (Si
3
N
4
) may need to remain on the top and sides of a gate or wires. As a result, in order to obtain an adequate selectivity when forming a contact hole by SAC etching, it may be desirable to increase the thickness of a hard mask or of a spacer, formed of silicon nitride (Si
3
N
4
). This may cause the aspect ratio of the contact hole to further increase.
Due to the increase in the aspect ratio of the contact hole, it may be more difficult to obtain a sufficient bottom critical dimension of the contact hole. As a result, a defect may occur, in which the hole does not open properly. However, it may be difficult to avoid an increase in the aspect ratio due to the above insulating shoulder.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide methods of conductively contacting an integrated circuit including a plurality of spaced apart lines thereon, using a dummy dielectric layer. In particular, a dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines. Accordingly, embodiments of the invention can reduce and preferably prevent electrical short circuits, and also can reduce and preferably prevent the likelihood of a contact hole not opening.
Other embodiments of the invention form a plurality of conductive lines, including a line-type conductive pattern and a shielding dielectric layer on sides and tops of the conductive pattern, on an integrated circuit substrate. A dummy dielectric layer is formed in gaps between the conductive lines. The dummy dielectric layer is patterned to produce a dummy opening that selectively exposes some of the gaps between the conductive lines. An interdielectric layer is formed, in the dummy opening. The dummy dielectric layer pattern is selectively removed using the interdielectric layer pattern as an etching mask, to form a contact opening. A conductive layer is formed in the contact opening and that is electrically connected to the substrate. The conductive layer is etched to separate the conductive layer into conductive contact bodies surrounded by the shielding dielectric layer and the interdielectric layer pattern.
According to still other embodiments, a conductive contact body of an integrated circuit device is formed, by forming a plurality of conductive lines including a line-type conductive pattern on a lower dielectric layer on an integrated circuit substrate, a spacer on the sides of the conductive pattern and a hard mask on tops of the conductive pattern. The lower dielectric layer is selectively etched using the hard mask and the spacer as an etching mask, to expose the substrate. A stopper layer is formed that covers the hard mask, the spacer, and the exposed substrate. A dummy dielectric layer is formed in gaps between the conductive lines on the stopper layer. The dummy dielectric layer is patterned to produce a dummy opening that selectively exposes some of the gaps between the conductive lines. An interdielectric layer pattern is formed in the dummy opening that selectively exposes the dummy dielectric layer. The dummy dielectric layer pattern is selectively removed using the interdielectric layer pattern as an etching mask, to form a contact opening that exposes the stopper layer beneath the dummy dielectric layer pattern. The stopper layer that is exposed by the contact opening is removed, and a conductive layer is formed in the contact opening and that is electrically connected to the substrate. The conductive layer is etched to separate the conductive layer into conductive contact bodies surrounded by the spacer and the interdielectric layer pattern.
Accordingly, embodiments of the present invention can reduce the likelihood of damaging a conductive pattern such as a gate or bit line. Embodiments of the invention also can reduce or prevent a spacer or a hard mask, which protects the sidewalls and/or tops of a conductive pattern, from being damaged while forming a conductive contact line.
REFERENCES:
patent: 5547900 (1996-08-01), Lin
patent: 6255160 (2001-07-01), Huang
patent: 6342452 (2002-01-01), Coronel et al.
patent: 6429107 (2002-08-01), Kim et al.
patent: 98-5439 (1998-03-01), None
Chu Chang-woong
Kim Dong-hyun
Kim Hyoung-joon
Kim Ji-soo
Lee Sang-hyeop
Coleman William David
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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