Methods for fabricating semiconductor devices having capacitors

Details Methods for fabricating semiconductor devices having capacitors Methods for fabricating semiconductor devices having capacitors

2002-12-17

2004-06-22

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06753221

ABSTRACT:

RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2001-85991, filed on Dec. 27, 2001, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices and, more particularly, to methods for fabricating semiconductor devices having capacitors.
2. Description of the Related Art
As integration levels of memory devices increase, the space taken up by a memory cell area is gradually decreased, resulting in a decrease in cell capacitance. To deal with this problem, much effort has been expended in the semiconductor industry. Such effort includes increasing surface areas of storage node electrodes or employing capacitor dielectric layers formed of a high-&kgr; material.
FIGS. 1
to
3
are cross-sectional views illustrating a conventional method for fabricating a semiconductor device having a capacitor.
Referring to
FIG. 1
, storage node plugs
104
are formed in a predetermined region of the semiconductor substrate
100
through an interlayer insulation layer
102
covering a semiconductor substrate
100
. The storage node plugs
104
are connected to a transistor formed under the interlayer insulation layer
102
, although not shown. A storage node electrode
106
is formed on each storage node plug
104
. The storage node electrode
106
is formed as high as possible to increase the cell capacitance. Thereafter, a capacitor dielectric layer
108
is conformally formed on the storage node electrodes
106
. The capacitor dielectric layer is typically composed of a material with a high dielectric constant, for example, tantalum oxide or aluminum oxide, so as to increase the cell capacitance.
Then, a plate electrode layer
110
is formed on the capacitor dielectric layer
108
. The plate electrode layer
110
may be composed of an element of the platinum group to improve leakage current characteristics of the capacitor dielectric layer
108
having a high dielectric constant.
Referring to
FIG. 2
, a photoresist pattern
116
is formed on the plate electrode layer
110
. The photoresist pattern
116
corresponds to an etch mask for forming a storage electrode according to predetermined regions of a cell array. The plate electrode layer
110
is patterned to form a plate electrode
110
p
using the photoresist pattern
116
as an etch mask. The plate electrode layer
110
, composed of an element of the platinum group, has a low etch rate and reacts on an etch gas to form a hard polymer fence or etch byproducts
118
at etch boundaries.
Referring to
FIG. 3
, the photoresist pattern
116
is removed to expose the plate electrode
110
p
. As illustrated in
FIG. 3
, in the conventional method, the gap between the storage node electrodes
106
, covered with the plate electrode
110
p
, has a high aspect ratio. As a result, a residue or scum
126
may remain in the gap. The greater the height of the storage node electrode
106
gets to increase surface areas of the storage node electrode
106
, the more the residue
126
is likely to remain in the gap. Besides, in an ashing process for removing the photoresist pattern
116
, a residue of the hard polymer fence
118
may remain at the boundaries of the plate electrode
110
p
. Thus, the remaining polymer fence
118
can become a contamination source in subsequent processes.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a semiconductor device having a capacitor in which residue materials do not remain in a gap between adjacent storage node electrodes after forming a plate electrode.
The present invention also provides a method for fabricating a semiconductor device having a capacitor, which can remove polymer remaining at boundaries of the plate electrode after forming a plate electrode, without attacking the plate electrode.
According to an embodiment of the present invention, a plurality of storage node electrodes are formed in a predetermined region of a semiconductor substrate. A capacitor dielectric layer is then formed to conformally cover the storage node electrodes and the plate electrode layer is formed on the capacitor dielectric layer.
Then, a gap between the storage node electrodes is filled, using methods such as forming a hard mask layer on the resultant structure where the plate electrode layer is formed. The hard mask layer and the plate electrode layer are successively etched to form a plate electrode.
In accordance with another embodiment of the present invention, photoresist residues, which may remain in a gap between adjacent storage nodes due to a gap's high aspect ratio, can be prevented, while forming a plate electrode. Besides, when a plate electrode is composed of an element of a platinum group to improve leakage current characteristics of a high&kgr;-dielectric material, hard polymer, which may remain at boundaries of the plate electrode, can be effectively removed.


REFERENCES:
patent: 5780338 (1998-07-01), Jeng et al.
patent: 6222722 (2001-04-01), Fukuzumi et al.
patent: 6403444 (2002-06-01), Fukuzumi et al.
patent: 6479343 (2002-11-01), Hwang et al.
patent: 6583006 (2003-06-01), Ping
patent: 6590229 (2003-07-01), Yamazaki et al.
patent: 2002/0019107 (2002-02-01), Lin et al.
patent: 2000-101043 (2000-07-01), None
patent: 2000-45343 (2000-07-01), None
English Language of Abstract for Korean Patent Publication No. 2000-45343, filed Jul. 15, 2000.
English Language of Abstract for Japanese Patent Publication No. 2000-101043, filed Jul. 4, 2000.

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