Methods for fabricating interconnect structures having Low K...

Details Methods for fabricating interconnect structures having Low K... Methods for fabricating interconnect structures having Low K...

2001-12-27

2003-11-25

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S633000

Reexamination Certificate

active

06653224

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor structures, and more specifically to the fabrication of copper, LowK dielectric, dual damascene structures.
2. Description of the Related Art
In the fabrication of semiconductor devices, integrated circuits are defined on semiconductor wafers by forming a plurality of layers over one another resulting in multi-level structures. As a result of the various layers disposed over one another, a surface topography of the wafer can become irregular, and an un-corrected irregularity increases with the number of subsequent layers deposited. Chemical Mechanical Planarization (CMP) has developed as a fabrication operation primarily utilized to planarize the surface topography of deposited layers, and to remove the overburden deposits. Additional fabrication operations including surface finish, buffing, insulator cleaning, etching, and the like, are also frequently accomplished using CMP processes and apparatus.
At the substrate level, transistor devices having diffusion regions are formed over and into silicon substrates. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide in conventional cases. At each metallization level there is a need to remove the overburden metal or to planarize dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other major applications, metallization line patterns are formed in the dielectric material, then conductive material is deposited over the whole wafer surface, and finally, metal a CMP operation is performed to remove excess metallization, e.g., such as copper. An additional diffusion layer is normally deposited prior to conductor deposition to prevent diffusion of conductive material into the bulk of dielectric that deteriorates its insulating dielectric properties and poisons the transistors.
Copper dual damascene technology, and the technology of conductive material dual damascene structures, evolved into a process of choice for the integrated circuit industry. In copper dual damascene fabrication, the Cu-CMP is typically utilized for both copper and barrier overburden removal, as described below in references to
FIGS. 1A-1C
.
FIG. 1A
shows a portion of a semiconductor wafer
10
with a typical copper dual damascene structure being fabricated therein. Features
14
such as trenches and vias have been fabricated into insulator
12
. A barrier
18
has been deposited over the insulator
12
lining the features
14
. Copper fill has been deposited in the features
14
resulting in copper overburden
16
over barrier
18
.
FIG. 1B
shows the portion of semiconductor wafer
10
with the copper dual damascene structure being fabricated therein described in
FIG. 1A
after a first CMP process has been performed. The first CMP is performed to planarize the surface of the insulator
12
at the barrier
18
. The copper overburden
16
shown in
FIG. 1A
is essentially removed, leaving only copper fill
16
′ in features
14
, and barrier
18
to make up the planarized surface. It should be appreciated that, up until the point of removal of the copper overburden (see
FIG. 1A
) exposing barrier
18
, the surface being planarized by CMP is a homogenous material. As soon as barrier
18
is exposed, the surface becomes heterogeneous with both copper fill
16
′ and barrier
18
material and chemical properties being processed by CMP.
FIG. 1C
shows an ideal completion of a dual damascene structure fabricated in a portion of a semiconductor wafer
10
. The ideal structure illustrated is the fabrication goal following a second CMP of the structure illustrated in FIG.
1
B. Barrier
18
(see
FIG. 1B
) is removed leaving a planarized insulator surface including the insulator
12
, a barrier liner
18
′ of features
14
, and the copper fill
16
′ within features
14
. It should be noted that number of materials with differing material and chemical properties processed by CMP in
FIG. 1C
is now three.
As is known, CMP was initially developed for, and is most effective and well suited for planarization of a non-planar homogenous (i.e., consisting of the same material) surface. Looking again at
FIG. 1B
, it should be appreciated that in final phases of the copper CMP, the surface is neither homogenous, nor is it in need of planarization. In typical copper dual damascene structure fabrication, CMP is the next process step to be performed on the structure, but it is not a structure well suited for CMP.
To planarize a surface, CMP implements a combination of chemical and abrasive action by applying a surface to be planarized against a processing surface having varying degrees of elasticity, varying degrees of abrasiveness, wetted with varying degrees of chemically aggressive slurry which also may contain varying degrees of abrasiveness, all according to process goals, process conditions, material and chemical properties, and the like. In the case of copper CMP, it is common practice to use a processing surface such as a pad with a high degree of hardness. Due to the typically hard insulator
12
underlying a copper dual damascene structure, pressure is generally also moderate to high, and the frictional contact generated between the processing surface and the surface to be planarized, results in generally high shear stress at the surface of the wafer.
Under the processing conditions just described, the point at which the copper overburden
16
(see
FIG. 1
) is removed and barrier
18
is exposed, the surface being processed by CMP is practically flat, however no longer homogenous, and the effectiveness of the CMP is dramatically reduced. Typically, it is at this point when the CMP process, and processing conditions are modified in order to remove barrier
18
with a second CMP process, but the heterogeneous surface including the hard barrier
18
and the soft copper
16
′ are not optimally processed by the same CMP operation. Instead of the ideal structure illustrated in
FIG. 1C
, a typical semiconductor wafer is processed less precisely and results in less than ideal structures therein.
FIG. 1D
illustrates a typical copper dual damascene structure reflecting structural flaws typical of heterogeneous CMP processing. CMP generally removes barrier
18
(see
FIG. 1B
) and leaves features
14
lined with barrier liner
18
′ and copper filled
16
′, but surface irregularities are noted such as dishing
20
in the copper fill
16
′, and a less than planar surface
22
across the structure. The less than planar surface
22
typically also includes dielectric erosion
24
. Additionally, because copper is a material of the structure, and it is a soft and reasonably chemically reactive material, preventing corrosion of the copper fill
16
′, and scratching, are also serious fabrication challenges.
What is needed are methods and apparatus for copper, and other conductive material, dual damascene structure fabrication that exploit the advantages of CMP for planarization of the homogenous part of the overburden material, which is copper, and implement alternative fabrication processes better suited for heterogeneous surface processing. The methods and apparatus should be implemented to maximize manufacturing efficiency, and position the technology of dual damascene to better introduce and develop emerging related technologies.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a method for forming dual damascene structures in LowK dielectric insulators that utilizes CMP for those processes in which CMP is most effective, and etch for those processes better suited for etch fabrication

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