Methods for fabricating field effect transistors having...

Details Methods for fabricating field effect transistors having... Methods for fabricating field effect transistors having...

2005-04-19

2005-04-19

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S344000, C257S345000, C257S346000

Reexamination Certificate

active

06881630

ABSTRACT:
Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.

REFERENCES:
patent: 4998150 (1991-03-01), Rodder et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5409853 (1995-04-01), Yu
patent: 5677214 (1997-10-01), Hsu
patent: 5760451 (1998-06-01), Yu
patent: 5780896 (1998-07-01), Ono
patent: 5908313 (1999-06-01), Chau et al.
patent: 5915183 (1999-06-01), Gambino et al.
patent: 5970352 (1999-10-01), Shiozawa et al.
patent: 6063676 (2000-05-01), Choi et al.
patent: 6114209 (2000-09-01), Chu et al.
patent: 6198142 (2001-03-01), Chau et al.

Affiliated with

Also associated with

Rating

Methods for fabricating field effect transistors having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for fabricating field effect transistors having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating field effect transistors having... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3407581