Methods and systems for dynamically selecting word line off...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S233100, C365S189070

Reexamination Certificate

active

10991729

ABSTRACT:
Methods for controlling the timing of a pre-charge operation in a memory device are provided. In embodiments of the present invention, the timing may be controlled by dynamically selecting a word line off time based on information about a number of column cycles. This may be accomplished, for example, by routing a word line disable signal via one of a first plurality of delay paths. The methods may further include dynamically selecting a bit line equalization start time based on the information about the number of column cycles. This may be accomplished, for example, by routing a bit line equalization start signal via one of a second plurality of delay paths. Pursuant to still further embodiments of the present invention, systems for controlling timing in a memory device are provided which include a control circuit that is configured to select a word line off time from a plurality of word line off times in response to a word line signal and information about a number of column cycles.

REFERENCES:
patent: 6788597 (2004-09-01), Ladner et al.
patent: 6865101 (2005-03-01), Iwanari
patent: 6967886 (2005-11-01), Huang et al.
patent: 2003/0191974 (2003-10-01), Kato et al.
patent: 2001-266570 (2001-10-01), None
patent: 000020619 (2000-04-01), None
patent: 1020020057284 (2002-07-01), None
patent: 2003-0080991 (2003-10-01), None
Notice to Submit Response, Korean Application No. 10-2003-0087535, Aug. 31, 2005.

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