Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2002-01-16
2004-07-06
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S326000, C430S327000, C430S329000
Reexamination Certificate
active
06759179
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing processes, and more particularly to methods and apparatus for controlling resist residue defects at Polysilicon Gate layer in a semiconductor device manufacturing process.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been and continue to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. The requirement of small features (and close spacing between adjacent features) requires high resolution lithographic processes. In general, lithography refers to processes for pattern transfer between various media It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist. The photoresist coated substrate is baked to evaporate any solvent in the photoresist composition and to fix the photoresist coating onto the substrate.
The baked coated surface of the substrate is next subjected to selective radiation using a mask, wherein the mask is employed to effect an image-wise exposure to actinic radiation. The masking step is used to protect one area of the wafer while working on another. Alignment apparatus aligns the wafer to the mask, and then projects an intense light through the mask and through a series of reducing lenses, exposing the photoresist with the mask pattern. The mask permits radiation to contact certain areas of the photoresist and prevents radiation from contacting other areas of the photoresist. This selective radiation exposure causes a chemical transformation in the exposed areas of the photoresist coated surface. Types of radiation commonly used in microlithographic processes include visible light, ultraviolet (UV) light, deep ultraviolet (DUV) light and electron beam radiant energy. After selective exposure, the photoresist coated substrate is treated with a developer solution to dissolve and remove either the radiation-exposed or the unexposed areas of the photoresist (depending upon whether a positive or a negative photoresist is utilized) resulting in a patterned or developed photoresist, exposing the underlying layer (e.g., oxide) previously deposited. The portions of the underlying layer not protected by the hardened resist layer may now be etched away, by, for example, a chemical solution or plasma gas discharge, or may otherwise be operated on.
Due to the large number of critical masking steps in a modem process flow and the inherent ability to impact pattern fidelity, photolithographic defects are particularly dangerous. The ability to detect and eliminate new defect types becomes increasingly important as integrated circuit device geometries continue to shrink into the deep sub-micron regime. Post-develop residue is a common defect phenomenon particularly in DUV lithography which occurs at a critical mask layer. For example, post-develop defects may occur at an active mask layer on a nitride film and/or at a Gate mask on a polysilicon/silicon oxide film or on a silicon nitride BARC (bottom anti-reflective coating) film.
Formation of post-develop or resist residue defects commonly occurs during a pattern image transfer associated with a lithography process. As a result of irradiating a photoresist through a photomask, resist residue or byproducts often form on the photoresist. A developer solution is then deposited over the selectively irradiated photoresist. However, the solubility of the radiation sensitive Photo Acid Generator (PAG) contained in the photoresist can be low. Moreover, it is believed that low solubility rates of the PAG in the developer are exacerbated by the presence of impurities (calcium, sulfur), which cause exposed (open) regions of the resist to be incompletely dissolved in the developer solution within a common process time (typically a 30 to 60 second develop time). As a result, circular defects are generated and remain on the wafer at the completion of the development cycle.
If the resist residue (resist byproducts) contains impurities, such as carbon, calcium (such as in the form of CaF), nitrogen and/or sulfur, the defects become robust enough to withstand decay during a subsequent Barc (bottom anti-reflective coating)/Polysilicon etch process. Hence, poor fidelity of the desired pattern at that layer results (the defects prevent processing of the underlying layer). These post-develop defects tend to have a circular appearance and thus are typically referred to as circular, satellite or cluster defects. Due to their subtle physical characteristics and low density, these defects are often dismissed as non-fatal defects. However, they may contribute to yield loss and raise device reliability issues because of the sheer volume (hundreds to thousands) of such defects on the wafer. In addition, despite their subtle physical characteristics, they can undesirably act as a hard mask, resulting in pattern deformation after etch. Thus, pattern deformation poses a substantial yield risk. In light of these problems, there is an unmet need for detecting, reducing and controlling the presence of post-develop defects at critical mask layers
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention, nor to delineate the scope of the present invention. Rather, the sole purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented hereinafter. The present invention provides methods and apparatus for controlling resist residue defects in a semiconductor device manufacturing process.
One aspect of the invention provides a method of reducing resist residue defects in a semiconductor manufacturing process, comprising performing a special vapor prime operation to a semiconductor substrate structure, applying a photoresist coat to the semiconductor substrate structure, and selectively exposing a first portion of the photoresist coat using an exposure source and a photomask, wherein a second portion of the photoresist is unexposed. The method further comprises performing a special development operation on the first portion of the photoresist using a developer, removing the developed first portion of the photoresist from the structure, and removing resist residues from the structure in order to reduce resist residue defects. The vapor prime operation comprises priming the structure using an HDMS type priming agent at a temperature from about 85 degrees C. or more to about 130 degrees C. or less for a time period from about 5 seconds or more to about 20 seconds or less.
The development operation comprises dispensing developer onto a semiconductor substrate structure, rinsing front and back sides of the semiconductor substrate structure while spinning the semiconductor substrate structure at a medium speed for a first time period, rinsing the front and back sides of the semiconductor substrate structure while spinning the semiconductor substrate structure at a low speed for a second time period, rinsing the front side of the semiconductor substrate structure for a third time period, and drying the semiconductor substrate structure while spinning the semiconductor substrate structure at a high speed. The development is performed while maintaining a high exhaust air velocity, and may employ extended rinse times, in order to mitigate resist residue defects in the process.
REFERENCES:
patent: 6649525 (2003-11-01), Phan et al.
“Understanding the DUV Resist Development Process Using A Develop Residue Monitoring Technique”. C. Pike and J Erhardt. Presented at Interface 1999; Microlithography Sym
Bartlett Richard J.
Bradway Carol M.
Cheng Jerry
Coniglio Anthony P.
Erhardt Jeffrey
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Huff Mark F.
Ruggles J.
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