Methods and apparatus for the optimization of etch...

Etching a substrate: processes – Gas phase etching of substrate – Application of energy to the gaseous etchant or to the...

Reexamination Certificate

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C216S051000, C216S067000, C216S072000, C216S079000, C216S080000, C216S104000, C438S710000, C438S723000, C438S724000, C438S743000, C438S744000

Reexamination Certificate

active

10883282

ABSTRACT:
In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

REFERENCES:
patent: 5482749 (1996-01-01), Telford et al.
patent: 5571576 (1996-11-01), Qian et al.
patent: 5647953 (1997-07-01), Williams et al.
patent: 6071573 (2000-06-01), Koemtzopoulos et al.
patent: 6274500 (2001-08-01), Xuechun et al.
patent: 6325948 (2001-12-01), Chen et al.
patent: 6420274 (2002-07-01), Baker et al.
patent: 6455333 (2002-09-01), Kathuria
patent: 6613689 (2003-09-01), Liu et al.
patent: 6626187 (2003-09-01), Yang et al.
patent: 6869542 (2005-03-01), Desphande et al.
S.Wolf, Silicon Processing for the VLSI Era, vol. 1, Lattice Press, (1986), p. 581.
S.Wolf, Silicon Processing for the VLSI Era, vol. 4, Lattice Press (2002), pp. 245-246.
Rossnagel, Handbook of Plasma Processing Technology, Noyes Publishers (1990), p. 207.
Wolf, S., Silicon Processing for the VLSI Era, (2002) vol. 4, pp. 245 & 654.
International (PCT) Search Report, mailed Nov. 6, 2006, re PCT/US05/21047.
Written Opinion, mailed Nov. 6, 2006, re PCT/US05/21047.
Mui et al., “Integrated Optical Metrology Controls Post-Etch CDs”, Jun. 2002, Semiconductor International, http://www.reed-electronics.com/semiconductor/article/CA218630.
Braun, Alexander E., “Resist Technology Concentrates on 248 nm”, Feb. 2003, Semiconductor International, http://static.highbeam.com/s/semiconductorinternational/february012003/resisttechnologyconcentrateson248nm/.
Bergeron, David, “Resolution Enhancement Techniques for the 90-nm Technology Node and Beyond”, Jul. 2003, Future Fab Intl., vol. 15.
International Preliminary Report on Patentability (IPRP), mailed Jan. 18, 2007, regarding PCT/US2005/021047.

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