Methods and apparatus for testing a scan chain to isolate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S006130, C714S030000, C714S738000, C326S016000, C324S073100

Reexamination Certificate

active

10708380

ABSTRACT:
Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 4945536 (1990-07-01), Hancu
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5617430 (1997-04-01), Angelotti et al.
patent: 5784382 (1998-07-01), Byers et al.
patent: 6223312 (2001-04-01), Nozuyama
patent: 6308290 (2001-10-01), Forlenza et al.
patent: 6490702 (2002-12-01), Song et al.
patent: 6516432 (2003-02-01), Motika et al.
patent: 6622273 (2003-09-01), Barnes
E.B. Eichelberger, et al, “A Logic Design Structure for LSI Testability”, Proceedings of the Fourteenth Design Automation Conference, New Orleans, 1977, pp. 462-468.
David P. Vallett, “IC Failure Analysis: The Importance of Test and Diagnostics”, IEEE Design & Test of Computers, Jul.-Sep. 1997, pp. 76-82.
James L. Schafer et al. “Partner SRLS for Improved Shift Register Diagnostics”, IEEE VLSI Test Symposium, Jun. 1992, pp. 198-200.
Sandip Jundu, “Diagnosing Scan Chain Faults”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 2, No. 4, Dec. 1994, pp. 512-517.
Samantha Edirisooriya et al., “Diagnosis of Scan Path Failures”, Proceedings of IEEE VLSI Test Symposium Apr. 1995, pp. 250-255.
Sridhar Narayanan et al., “An Efficient Scheme to Diagnose Scan Chains”, International Test Conference, Jul. 1997, pp. 704-713.

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