Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-10-26
2010-06-22
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07743298
ABSTRACT:
In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.
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Bhatia Sandeep
Roig Oriol
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Chung Phung M
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