Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-06-17
2010-02-23
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
07669096
ABSTRACT:
Apparatus and methods are provided for debugging an integrated circuit. Local multiplexer circuits are provided near first and second circuit blocks in the integrated circuit. Each multiplexer circuit includes input nodes, a control node, and an output node. A first input node of the first multiplexer circuit is coupled to an internal node of the first circuit block, a first input node of the second multiplexer circuit is coupled to an internal node of the second circuit block, second input nodes of the first and second multiplexer circuits are coupled to logical 0, and the control signal nodes of the first and second multiplexer circuits are coupled to a control signal. An OR gate is provided that includes an input node coupled to the output node of the first multiplexer circuit, another input node coupled to the output node of the second multiplexer circuit, and an output node. The control signal is used to select the internal nodes of the first or second circuit blocks for monitoring at the output node of the OR gate.
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Electronics for Imaging, Inc.
Glenn Michael A.
Glenn Patent Group
Ton David
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