Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-18
2007-09-18
Lamarre, Guy (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S741000, C714S732000, C714S724000, C714S718000, C324S765010, C365S201000
Reexamination Certificate
active
11117893
ABSTRACT:
Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are selected. Each of the IDDQ vectors are identified in a test pattern. During subsequent testing, an IDDQ test of the semiconductor chip can be performed whenever the current test vector applied by the logic BIST corresponds to one of the predetermined IDDQ states. A single test pattern based upon vectors generated by the logic BIST module can therefore be used to perform both IDDQ and stuck-at testing.
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Benecke Loren J.
Colunga Tomas V.
Mahadevan Sribhaskar
Vaccaro Joseph S.
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz
Lamarre Guy
Trimmings John P
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