Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-11-17
2002-06-18
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S798000
Reexamination Certificate
active
06407007
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method used to fabricate a semiconductor device, and more specifically to a method used to form passivating insulator layers on underlying metal interconnect structures.
(2) Description of Prior Art
The trend in the semiconductor industry has been to continually increase device performance, while still maintaining or decreasing the cost of semiconductor devices. These objectives have been partially satisfied by micro-miniaturazation, or the ability to produce semiconductor devices with sub-micron features. Advances in the photolithographic discipline, in terms of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials have allowed sub-micron images in photoresist to be routinely achieved. In addition similar advances in the dry etching discipline has allowed the sub-micron images in photoresist to be successfully defined, in underlying materials that are used in the fabrication of semiconductor chips.
The use of sub-micron features however, can however create new problem areas that have to be addressed by the semiconductor engineering community. For example when using a technology with a minimum feature of 0.25 um, the use of sub-micron metal interconnects, with sub-micron spaces between metal interconnects, has created a problem in terms of using standard dielectric passivation processes, used to successfully insulate specific metal interconnects. To satisfy the conductivity, as well as the reliability requirements, in terms of current density for electromigration resistance, the narrower metal interconnects have to be thicker. This together with the narrower spaces, now used between metal lines, result in aspect ratios that conventional insulator deposition processes have difficulty in successfully filling. However the use of spin on glass, (SOG), layers, have been successful in passivating the thicker, narrow metal interconnects structures, in terms of the ability of the SOG layer to fill the narrow spaces between the metal interconnect structures. The SOG layer, applied via a technology similar to photoresist application, results in a planar top surface, featuring a thick SOG, in the narrow spaces between metal structures, while a thinner SOG layer is formed on the top surface of the narrow metal interconnect structures.
To successfully complete the passivation of underlying conductive elements, of a sub-micron semiconductor device, a thick silicon nitride layer is used, overlying the SOG layer. However the adhesion of the thick silicon nitride layer, on an underlying SOG layer, can be marginal, sometimes resulting in deleterious delamination of the thick silicon nitride layer. This invention will offer a solution to the unwanted phenomena of silicon nitride delamination, from underlying SOG layers. This is accomplished via use of a novel nitrous oxide anneal procedure, performed in situ, prior to the deposition of the thick silicon nitride layer. Prior art, such as Pan et al, in U.S. Pat. No. 5,556,806, offers an oxygen plasma treatment of a SOG layer, prior to deposition of overlying layers, while Chang, in U.S. Pat. No. 5,643,407, describes a method of subjecting a via hole, formed in a SOG, layer, to a nitrogen plasma treatment, prior to filling the via hole with metal. However these prior arts do not describe the in situ, nitrous oxide procedure, offered in this invention, applied to an underlying SOG layer, prior to deposition of a thick silicon nitride layer.
SUMMARY OF THE INVENTION
It is an object of this invention to use a SOG layer to passivate underlying metal interconnect structures, and to fill the narrow spaces between metal interconnect structures.
It is another object of this invention to use a thick silicon nitride layer on the underlying SOG layer.
It is yet another object of this invention to perform a plasma anneal treatment of the underlying SOG layer, in a nitrous oxide plasma, prior to the in situ deposition of an overlying, thick silicon nitride layer.
In accordance with the present invention a method is described for forming a silicon nitride layer on a SOG layer, where the SOG layer is located on, and in the narrow spaces between, metal interconnect structures, and featuring the use of a plasma nitrous oxide anneal procedure, prior to the in situ deposition of the silicon nitride layer. After formation of the metal interconnect structures, on an underlying, first insulator layer, and with the metal interconnect structures communicating with underlying conductive elements, through via holes in the first insulator layer, exposing the underlying conductive elements, a second insulator layer is conformally deposited on the metal interconnect structures, and in the spaces between metal interconnect structures, however not filling the spaces between the metal interconnect structures. A spin on glass, (SOG), layer is next applied, completely filling the spaces between the metal interconnect structures, and resulting in a planar top surface topography. A plasma, nitrous oxide treatment is next applied to the exposed planar SOG surface, followed by an in situ deposition of a thick silicon nitride layer.
REFERENCES:
patent: 5314839 (1994-05-01), Mizutani et al.
patent: 5554567 (1996-09-01), Wang
patent: 5556806 (1996-09-01), Pan et al.
patent: 5567658 (1996-10-01), Wang et al.
patent: 5643407 (1997-07-01), Chang
patent: 5650359 (1997-07-01), Ahlburn
patent: 5665849 (1997-09-01), Cho
patent: 5861345 (1999-01-01), Chou et al.
patent: 5989983 (1999-11-01), Goo et al.
patent: 6143670 (2000-11-01), Cheng et al.
patent: 6153512 (2000-11-01), Chang et al.
patent: 6184123 (2001-02-01), Ge et al.
Wolf et al., Silicon Processing for the VLSI Era vol. 1, Lattice Press, 1986, p. 191.*
Djennas F. et al., Investigation of Plasma Effects on Plastic Packages Delamination and Cracking. 1993, IEEE, pp. 919-924.
Lan Chin Kun
Tsan Chun-Ching
Wang Hui-Ling
Wang Ying-Lang
Ackerman Stephen B.
Chaudhuri Olik
Duy Mai Anh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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