Method to remove spacer after salicidation to enhance...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S201000, C257SE27046

Reexamination Certificate

active

07445978

ABSTRACT:
An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

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patent: 2005/0112817 (2005-05-01), Cheng et al.
patent: 2006/0199326 (2006-09-01), Zhu et al.
patent: 2006/0234455 (2006-10-01), Chen et al.

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