Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-11
2003-04-15
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S770000
Reexamination Certificate
active
06548363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of manufacture of electronics devices. More particularly, the present invention relates to the field of fabrication of complementary metal-oxide-silicon field effect transistor devices in microelectronics fabrications.
2. Description of the Related Art
In the field of electronics devices, there is considerable interest in complementary metal-oxide-silicon (CMOS) field effect transistor (FET) devices employed within microelectronics fabrications. The CMOS approach connects FET devices of opposite p- and n-type polarity together into binary or “flip-flop” circuits and permits the manufacture of integrated circuit microelectronics fabrications with extremely low power consumption since there is essentially no current flow except during actual switching of the circuits from one state to the other.
Along with the CMOS design and its inherently low power consumption, it is also desirable to have a low drain leakage current for the individual FET device in a CMOS application, along with low threshold switching voltage and high gain, to further minimize power consumption. In general, these desired features are available in conventional FET devices and CMOS circuits due to increasingly smaller dimensions; in particular, gate oxide insulation layers are formed as thin as practicable within the limits of dielectric breakdown and device yield to reduce threshold voltages and increase device current gain. Although practical CMOS FET devices may be fabricated to approach these desired performance limits, such devices are not without problems.
In deep sub-micron CMOS FET devices, the gate induced drain leakage (GIDL) current increases because the gate oxide insulation layer thickness is reduced to as low as 40 angstroms. Gate induced leakage current may be reduced by forming a thicker gate oxide at the gate edge (“bird's beak”) employing thermal oxidation after gate definition. While thus reducing gate induced leakage current, such designs present other problems in fabrication and device operation.
It is thus towards the goal of reducing drain leakage current in FET devices that the present invention is generally directed. More particularly, it is towards the goal of reduction of gate induced drain (GIDL) leakage current in CMOS FET devices that the present invention is more specifically directed.
Various methods have been disclosed for the control of drain leakage and other leakage currents as well as other parameters in FET devices.
For example, Hayden et al., in U.S. Pat. No. 5,371,026, disclose a method for forming coupled MOS FET devices in which the current gain of the first device exceeds that of the second device. The method employs differential formation of thicker silicon oxide gate oxide insulating layer at the edge of one transistor but not the other, resulting in a higher channel resistance and hence lower current gain in the first device.
Further, Hong et al., in U.S. Pat. No. 5,498,556, disclose a method for forming a MOS FET device with reduced gate induced drain leakage current and reduce drain overlap region capacitance. The method employs oxidation of the gate electrode and substrate to produce thicker silicon oxide gate oxide at the edges of the gate electrode, followed by complete removal of the silicon oxide from the region beyond the gate electrode and implantation of source and drain regions. Subsequent angled ion implantation forms source and drain extensions under the edges of the gate electrode, minimizing overlap capacitance.
Still further, Sun et al., in U.S. Pat. No. 5,834,346, disclose a method for preventing formation of gas bubbles over source-drain regions in p-channel MOSFET devices. The bubbles are caused by outgassing of implanted species such as BF
2
+
into subsequently deposited glass layers during reflow. The method partially replaces the plasma etch process which contributes to the adsorption of BF
2
+
with a wet etch process to mitigate the adsorption of BF
2
+
Still further yet, Hsieh et al. in U.S. Pat. No. 5,858,840, disclose a method for forming a split-gate FET flash memory cell with increased erase speed. The method employs the selective implantation of nitrogen ions such that the floating gate region, which is not implanted, oxidizes faster to form a thicker silicon oxide region or “bird's beak” of a sharper shape at the edge of the floating gate, resulting in an increase in erase speed of the memory cell.
Yet still further, Fang et al., in U.S. Pat. No. 5,858,844, disclose a method for forming an FET device with optimized performance. The method employs an oxidation of the polycrystalline silicon gate electrode to increase the silicon oxide gate oxide insulation thickness at the edge of the gate electrode. Subsequently the source and drain regions are formed by ion implantation.
Yet further still, Hsieh et al., in U.S. Pat. No. 5,879,992, disclose a method for forming a split-gate FET flash memory cell with improved performance. The method employs a step polycrystalline silicon layer and a dielectric spacer layer formed between the step polysilicon layer and a control gate electrode.
Finally, Chiang et al., in U.S. Pat. No. 5,915,178, disclose a method for forming a FET flash memory cell for an electronically programmable read-only memory which has increased longevity of switching cycles. The method employs a shallow arsenic heavily doped source region adjacent to the floating gate and control gate region.
Desirable in the art of microelectronics fabrication are further methods for forming CMOS FET devices with reduced drain leakage and other leakage currents, and in particular methods for reducing gate induced drain leakage (GIDL) current.
It is towards these goals that the present invention is generally and more specifically directed.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a field effect transistor (FET) device with reduced leakage current.
It is a second object of the present invention to provide a method in accord with the first object of the present invention where there is formed within a silicon semiconductor substrate employed within an integrated circuit microelectronics fabrication complementary metal-oxide-silicon (CMOS) field effect transistor (FET) devices with attenuated gate induced drain leakage current, short channel effect and punch-through leakage current.
It is a third object of the present invention to provide a method in accord with the first object of the present invention and/or the second object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming FET devices with attenuated drain leakage current. To practice the invention, there is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon semiconductor substrate field oxide (FOX) dielectric isolation regions defining an active device area of the silicon substrate. There is formed over the silicon substrate in the active device area a silicon oxide gate oxide dielectric layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide dielectric layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the silicon substrate and gate electrode to form a thicker silicon oxide gate oxide dielectric layer at the edge of the patterned polycrystalline silicon gate electrode layer and in the adjacent silicon substrate area. There is then etched back the silicon oxide dielectric layer from the silicon substrate region beyond the gate electrode employing an anisotropic self-aligned etch process. There is then formed shallow junction source-drain extension (SDE) regions adjacent to the gate electrode by low energy ion implantation. There are then form
Diaz Carlos Hernando
Lin Bi-Ling
Wu Chung-Cheng
Ackerman Stephen B.
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
Trinh Michael
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